AurelienUoU cc0bfdd548 Add testcase in regression test for architecture with 1 IO cell/IO block		2019-09-20 10:27:26 -06:00
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k6_N10_sram_chain_HC_1IO_template.xml	Add testcase in regression test for architecture with 1 IO cell/IO block	2019-09-20 10:27:26 -06:00
k6_N10_sram_chain_HC_DPRAM_template.xml	Added architecture and replaced variables	2019-08-19 19:02:50 -06:00
k6_N10_sram_chain_HC_behavioral_verilog_template.xml	add more testing architecture	2019-08-27 18:44:58 -06:00
k6_N10_sram_chain_HC_local_encoder_template.xml	add more testing tasks	2019-08-23 10:16:52 -06:00
k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml	add non-LUT intermediate buffer to test and apply minor bug fix	2019-09-18 15:04:51 -06:00
k6_N10_sram_chain_HC_template.xml	Added architecture and replaced variables	2019-08-19 19:02:50 -06:00
k6_N10_sram_chain_HC_tileable_template.xml	add tileable routing to regression test	2019-09-16 20:45:02 -06:00
k6_N10_sram_chain_HC_tree_mux_template.xml	add non-LUT intermediate buffer to test and apply minor bug fix	2019-09-18 15:04:51 -06:00
k8_N10_sram_chain_FC_template.xml	add non-LUT intermediate buffer to test and apply minor bug fix	2019-09-18 15:04:51 -06:00