AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches		2019-05-21 17:24:06 -06:00
..
convert_blif.pl	Update on the examples to respect the new syntax	2018-11-19 15:50:29 -07:00
fpga_arch_gen.pl	Config script written and changed some rights for some files	2018-10-24 15:59:32 -06:00
fpga_flow.pl	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
generate_config.pl	and in the config path as well	2018-12-06 14:57:32 -07:00
m2net.pl	Config script written and changed some rights for some files	2018-10-24 15:59:32 -06:00
pro_blif.pl	Config script written and changed some rights for some files	2018-10-24 15:59:32 -06:00
run_fpga_spice.pl	Config script written and changed some rights for some files	2018-10-24 15:59:32 -06:00
run_multi.pl	Config script written and changed some rights for some files	2018-10-24 15:59:32 -06:00
tags	Update on the examples to respect the new syntax	2018-11-19 15:50:29 -07:00