tangxifan fd80cacaa3 [Flow] Add example script for behaviorial verilog generation		2020-11-22 21:14:10 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Bug fix in the and2_or2 benchmark	2020-09-17 10:35:13 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Edits to enable basic run_fpga_flow.py	2020-10-02 10:18:10 -04:00
openfpga_arch	[Arch] Add openfpga arch for using global clocks from tiles	2020-11-10 19:20:08 -07:00
openfpga_cell_library	[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals	2020-11-22 20:53:32 -07:00
openfpga_shell_scripts	[Flow] Add example script for behaviorial verilog generation	2020-11-22 21:14:10 -07:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	Merge pull request #104 from lukefahr/disp_fix	2020-10-07 09:54:06 -06:00
tasks	[Flow] disable signal initialization for behavioral verilog generation	2020-11-22 21:13:22 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Add k4 arch using global clock from tile port (with zero fc)	2020-11-10 19:17:34 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00