tangxifan 5aa206e616 [core] fixed some bugs		2023-09-25 22:27:24 -07:00
..
global_tile_4clock/config	[Test] Adapt pin constraints due to changes in pin names	2022-02-15 16:06:46 -08:00
global_tile_4clock_pin/config	[Test] Add a test case to validate separated clock pins in global port	2022-03-20 11:02:07 +08:00
global_tile_clock/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
global_tile_clock_subtile/config	[test] add a new testcase to validate subtile with tile annotations	2023-08-18 21:37:15 -07:00
global_tile_clock_subtile_port_merge/config	[test] add a new test to validate the tile port merge feature	2023-09-25 18:34:34 -07:00
global_tile_clock_subtile_port_merge_fabric_tile_group_config/config	[core] fixed some bugs	2023-09-25 22:27:24 -07:00
global_tile_reset/config	[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases	2022-09-29 10:45:27 -07:00