42 lines
2.1 KiB
Markdown
42 lines
2.1 KiB
Markdown
# Getting Started with FPGA-SPICE
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Clone the [OpenFPGA git repository:](https://github.com/LNIS-Projects/OpenFPGA)
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[//todo]: # (change to final repository location)
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`git clone https://github.com/LNIS-Projects/OpenFPGA.git `
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There is a submodule in the repository so move to the OpenFPGA directory and clone that too:
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`cd OpenFPGA`
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`git submodule init`
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`git submodule update`
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Go to the `VPR` directory and build the tool:
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`cd ./vpr7_x2p/vpr/`
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`make `
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Note: if you are using macOS, the graphical interface might not be usable since it requires the X11 library. In this case, open the Makefile and change the line 10 "ENABLE_GRAPHICS = true" to false.
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VPR requires a minimum of one XML file that specifies the architecture of the FPGA, and one BLIF file that specifies the logic circuit to be put on the FPGA.
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[//todo]: # (make sure the circuits are available)
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While in the `vpr` directory, run the tool on some example files:
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`./vpr ../libarchfpga/arch/sample_arch.xml ./Circuits/s298_K6_N10_ace.blif `
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If a graphic environment is available, this will bring up a display of how the circuit is being placed on the FPGA. Press the `Proceed` button to step to the final placement, press `Proceed` again to step to the routing. Press the `Exit` button to exit the display.
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To run VPR without the display, use the command `-nodisp`
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`./vpr ../libarchfpga/arch/sample_arch.xml ./Circuits/s298_K6_N10_ace.blif -nodisp`
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VPR creates a number of files in the same location as the BLIF file when it is run. The `place` file shows how the circuit was placed on the FPGA; the `route` file shows how the logic was routed on the FPGA; the `net` file shows the wiring.
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Now that we know that VPR is working, we can move on to FPGA-SPICE.
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The first example we want to run is go.sh in the same folder as we already are.
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`./go.sh`
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By calling this script (if not modified), we call FPGA-SPICE on an architecture built on TSMC 40 nm node in typical conditions. By modifying the script, we can do different corners at the same time.
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This script creates the folder verily_test containing the bitstream and other informations on the circuit we implemented. |