tangxifan 1c634e4600 add missing task file for generate bitstream test case		2020-07-02 17:24:51 -06:00
..
OpenFPGAShellScripts	add bitstream generation only test case to CI	2020-07-02 16:31:22 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	update arch to support reset signal for SRAm	2020-06-11 19:31:14 -06:00
arch	add readme for architecture file naming	2020-07-01 09:54:13 -06:00
benchmarks	start using counter benchmark in regression tests	2020-06-11 19:31:15 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	update sample key	2020-06-27 15:01:12 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	add readme for OpenFPGA architecture naming	2020-07-01 10:27:21 -06:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	Added external_fabric_key_file key	2020-06-12 15:37:12 -06:00
tasks	add missing task file for generate bitstream test case	2020-07-02 17:24:51 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00