339 lines
13 KiB
C
Executable File
339 lines
13 KiB
C
Executable File
#include <math.h> /* Needed only for sqrt call (remove if sqrt removed) */
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#include "util.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph_util.h"
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#include "rr_graph2.h"
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#include "rr_graph_indexed_data.h"
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#include "read_xml_arch_file.h"
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/* mrFPGA: Xifan TANG */
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#include "mrfpga_globals.h"
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/* end */
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/******************* Subroutines local to this module ************************/
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static void load_rr_indexed_data_base_costs(int nodes_per_chan,
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t_ivec *** L_rr_node_indices, enum e_base_cost_type base_cost_type,
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int wire_to_ipin_switch);
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static float get_delay_normalization_fac(int nodes_per_chan,
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t_ivec *** L_rr_node_indices);
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static float get_average_opin_delay(t_ivec *** L_rr_node_indices,
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int nodes_per_chan);
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static void load_rr_indexed_data_T_values(int index_start,
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int num_indices_to_load, t_rr_type rr_type, int nodes_per_chan,
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t_ivec *** L_rr_node_indices, const t_segment_inf * segment_inf);
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/******************** Subroutine definitions *********************************/
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/* Allocates the rr_indexed_data array and loads it with appropriate values. *
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* It currently stores the segment type (or OPEN if the index doesn't *
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* correspond to an CHANX or CHANY type), the base cost of nodes of that *
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* type, and some info to allow rapid estimates of time to get to a target *
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* to be computed by the router. *
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*
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* Right now all SOURCES have the same base cost; and similarly there's only *
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* one base cost for each of SINKs, OPINs, and IPINs (four total). This can *
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* be changed just by allocating more space in the array below and changing *
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* the cost_index values for these rr_nodes, if you want to make some pins *
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* etc. more expensive than others. I give each segment type in an *
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* x-channel its own cost_index, and each segment type in a y-channel its *
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* own cost_index. */
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void alloc_and_load_rr_indexed_data(INP const t_segment_inf * segment_inf,
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INP int num_segment, INP t_ivec *** L_rr_node_indices,
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INP int nodes_per_chan, int wire_to_ipin_switch,
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enum e_base_cost_type base_cost_type) {
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int iseg, length, i, index;
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num_rr_indexed_data = CHANX_COST_INDEX_START + (2 * num_segment);
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rr_indexed_data = (t_rr_indexed_data *) my_malloc(
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num_rr_indexed_data * sizeof(t_rr_indexed_data));
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/* For rr_types that aren't CHANX or CHANY, base_cost is valid, but most *
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* * other fields are invalid. For IPINs, the T_linear field is also valid; *
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* * all other fields are invalid. For SOURCES, SINKs and OPINs, all fields *
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* * other than base_cost are invalid. Mark invalid fields as OPEN for safety. */
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for (i = SOURCE_COST_INDEX; i <= IPIN_COST_INDEX; i++) {
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rr_indexed_data[i].ortho_cost_index = OPEN;
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rr_indexed_data[i].seg_index = OPEN;
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rr_indexed_data[i].inv_length = OPEN;
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rr_indexed_data[i].T_linear = OPEN;
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rr_indexed_data[i].T_quadratic = OPEN;
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rr_indexed_data[i].C_load = OPEN;
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}
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rr_indexed_data[IPIN_COST_INDEX].T_linear =
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switch_inf[wire_to_ipin_switch].Tdel;
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/* X-directed segments. */
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for (iseg = 0; iseg < num_segment; iseg++) {
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index = CHANX_COST_INDEX_START + iseg;
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rr_indexed_data[index].ortho_cost_index = index + num_segment;
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if (segment_inf[iseg].longline)
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length = nx;
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else
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length = std::min(segment_inf[iseg].length, nx);
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rr_indexed_data[index].inv_length = 1. / length;
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rr_indexed_data[index].seg_index = iseg;
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}
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load_rr_indexed_data_T_values(CHANX_COST_INDEX_START, num_segment, CHANX,
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nodes_per_chan, L_rr_node_indices, segment_inf);
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/* Y-directed segments. */
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for (iseg = 0; iseg < num_segment; iseg++) {
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index = CHANX_COST_INDEX_START + num_segment + iseg;
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rr_indexed_data[index].ortho_cost_index = index - num_segment;
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if (segment_inf[iseg].longline)
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length = ny;
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else
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length = std::min(segment_inf[iseg].length, ny);
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rr_indexed_data[index].inv_length = 1. / length;
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rr_indexed_data[index].seg_index = iseg;
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}
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load_rr_indexed_data_T_values((CHANX_COST_INDEX_START + num_segment),
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num_segment, CHANY, nodes_per_chan, L_rr_node_indices, segment_inf);
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load_rr_indexed_data_base_costs(nodes_per_chan, L_rr_node_indices,
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base_cost_type, wire_to_ipin_switch);
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}
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static void load_rr_indexed_data_base_costs(int nodes_per_chan,
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t_ivec *** L_rr_node_indices, enum e_base_cost_type base_cost_type,
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int wire_to_ipin_switch) {
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/* Loads the base_cost member of rr_indexed_data according to the specified *
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* base_cost_type. */
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float delay_normalization_fac;
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int index;
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if (base_cost_type == DELAY_NORMALIZED) {
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delay_normalization_fac = get_delay_normalization_fac(nodes_per_chan,
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L_rr_node_indices);
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} else {
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delay_normalization_fac = 1.;
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}
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if (base_cost_type == DEMAND_ONLY || base_cost_type == DELAY_NORMALIZED) {
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rr_indexed_data[SOURCE_COST_INDEX].base_cost = delay_normalization_fac;
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/* rr_indexed_data[SOURCE_COST_INDEX].base_cost = 0; Xifan TANG: TODO: Update routing cost to 1*/
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rr_indexed_data[SINK_COST_INDEX].base_cost = 0.;
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rr_indexed_data[OPIN_COST_INDEX].base_cost = delay_normalization_fac;
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/*rr_indexed_data[OPIN_COST_INDEX].base_cost = 0.95; Xifan TANG: TODO: Update routing cost to 1*/
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#ifndef SPEC
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rr_indexed_data[IPIN_COST_INDEX].base_cost = 0.95
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* delay_normalization_fac;
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#else /* Avoid roundoff for SPEC */
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rr_indexed_data[IPIN_COST_INDEX].base_cost =
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delay_normalization_fac;
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#endif
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}
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else if (base_cost_type == INTRINSIC_DELAY) {
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rr_indexed_data[SOURCE_COST_INDEX].base_cost = 0.;
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rr_indexed_data[SINK_COST_INDEX].base_cost = 0.;
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rr_indexed_data[OPIN_COST_INDEX].base_cost = get_average_opin_delay(
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L_rr_node_indices, nodes_per_chan);
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rr_indexed_data[IPIN_COST_INDEX].base_cost =
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switch_inf[wire_to_ipin_switch].Tdel;
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}
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/* Load base costs for CHANX and CHANY segments */
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for (index = CHANX_COST_INDEX_START; index < num_rr_indexed_data; index++) {
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if (base_cost_type == INTRINSIC_DELAY)
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rr_indexed_data[index].base_cost = rr_indexed_data[index].T_linear
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+ rr_indexed_data[index].T_quadratic;
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else
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/* rr_indexed_data[index].base_cost = delay_normalization_fac /
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rr_indexed_data[index].inv_length; */
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rr_indexed_data[index].base_cost = delay_normalization_fac;
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/* rr_indexed_data[index].base_cost = delay_normalization_fac *
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sqrt (1. / rr_indexed_data[index].inv_length); */
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/* rr_indexed_data[index].base_cost = delay_normalization_fac *
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(1. + 1. / rr_indexed_data[index].inv_length); */
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}
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/* Save a copy of the base costs -- if dynamic costing is used by the *
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* router, the base_cost values will get changed all the time and being *
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* able to restore them from a saved version is useful. */
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for (index = 0; index < num_rr_indexed_data; index++) {
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rr_indexed_data[index].saved_base_cost =
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rr_indexed_data[index].base_cost;
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}
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}
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static float get_delay_normalization_fac(int nodes_per_chan,
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t_ivec *** L_rr_node_indices) {
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/* Returns the average delay to go 1 CLB distance along a wire. */
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const int clb_dist = 3; /* Number of CLBs I think the average conn. goes. */
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int inode, itrack, cost_index;
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float Tdel, Tdel_sum, frac_num_seg;
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Tdel_sum = 0.;
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for (itrack = 0; itrack < nodes_per_chan; itrack++) {
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inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, CHANX, itrack,
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L_rr_node_indices);
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cost_index = rr_node[inode].cost_index;
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frac_num_seg = clb_dist * rr_indexed_data[cost_index].inv_length;
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Tdel = frac_num_seg * rr_indexed_data[cost_index].T_linear
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+ frac_num_seg * frac_num_seg
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* rr_indexed_data[cost_index].T_quadratic;
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Tdel_sum += Tdel / (float) clb_dist;
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}
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for (itrack = 0; itrack < nodes_per_chan; itrack++) {
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inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, CHANY, itrack,
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L_rr_node_indices);
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cost_index = rr_node[inode].cost_index;
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frac_num_seg = clb_dist * rr_indexed_data[cost_index].inv_length;
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Tdel = frac_num_seg * rr_indexed_data[cost_index].T_linear
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+ frac_num_seg * frac_num_seg
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* rr_indexed_data[cost_index].T_quadratic;
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Tdel_sum += Tdel / (float) clb_dist;
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}
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return (Tdel_sum / (2. * nodes_per_chan));
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}
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static float get_average_opin_delay(t_ivec *** L_rr_node_indices,
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int nodes_per_chan) {
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/* Returns the average delay from an OPIN to a wire in an adjacent channel. */
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/* RESEARCH TODO: Got to think if this heuristic needs to change for hetero, right now, I'll calculate
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* the average delay of non-IO blocks */
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int inode, ipin, iclass, iedge, itype, num_edges, to_switch, to_node,
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num_conn;
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float Cload, Tdel;
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Tdel = 0.;
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num_conn = 0;
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for (itype = 0; itype < num_types && &type_descriptors[itype] != IO_TYPE;
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itype++) {
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for (ipin = 0; ipin < type_descriptors[itype].num_pins; ipin++) {
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iclass = type_descriptors[itype].pin_class[ipin];
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if (type_descriptors[itype].class_inf[iclass].type == DRIVER) { /* OPIN */
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inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, OPIN,
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ipin, L_rr_node_indices);
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num_edges = rr_node[inode].num_edges;
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for (iedge = 0; iedge < num_edges; iedge++) {
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to_node = rr_node[inode].edges[iedge];
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to_switch = rr_node[inode].switches[iedge];
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Cload = rr_node[to_node].C;
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Tdel += Cload * switch_inf[to_switch].R
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+ switch_inf[to_switch].Tdel;
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num_conn++;
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}
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}
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}
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}
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Tdel /= (float) num_conn;
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return (Tdel);
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}
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static void load_rr_indexed_data_T_values(int index_start,
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int num_indices_to_load, t_rr_type rr_type, int nodes_per_chan,
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t_ivec *** L_rr_node_indices, const t_segment_inf * segment_inf) {
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/* Loads the average propagation times through segments of each index type *
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* for either all CHANX segment types or all CHANY segment types. It does *
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* this by looking at all the segments in one channel in the middle of the *
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* array and averaging the R and C values of all segments of the same type *
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* and using them to compute average delay values for this type of segment. */
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int itrack, iseg, inode, cost_index, iswitch;
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float *C_total, *R_total; /* [0..num_rr_indexed_data - 1] */
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int *num_nodes_of_index; /* [0..num_rr_indexed_data - 1] */
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float Rnode, Cnode, Rsw, Tsw;
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num_nodes_of_index = (int *) my_calloc(num_rr_indexed_data, sizeof(int));
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C_total = (float *) my_calloc(num_rr_indexed_data, sizeof(float));
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R_total = (float *) my_calloc(num_rr_indexed_data, sizeof(float));
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/* Get average C and R values for all the segments of this type in one *
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* channel segment, near the middle of the array. */
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for (itrack = 0; itrack < nodes_per_chan; itrack++) {
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inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, rr_type, itrack,
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L_rr_node_indices);
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cost_index = rr_node[inode].cost_index;
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num_nodes_of_index[cost_index]++;
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C_total[cost_index] += rr_node[inode].C;
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R_total[cost_index] += rr_node[inode].R;
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}
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for (cost_index = index_start;
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cost_index < index_start + num_indices_to_load; cost_index++) {
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if (num_nodes_of_index[cost_index] == 0) { /* Segments don't exist. */
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rr_indexed_data[cost_index].T_linear = OPEN;
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rr_indexed_data[cost_index].T_quadratic = OPEN;
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rr_indexed_data[cost_index].C_load = OPEN;
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} else {
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Rnode = R_total[cost_index] / num_nodes_of_index[cost_index];
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Cnode = C_total[cost_index] / num_nodes_of_index[cost_index];
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/* mrFPGA: Xifan TANG */
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if (is_isolation) {
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Cnode += switch_inf[iswitch].Cin + switch_inf[iswitch].Cout;
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}
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/* end */
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iseg = rr_indexed_data[cost_index].seg_index;
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iswitch = segment_inf[iseg].wire_switch;
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Rsw = switch_inf[iswitch].R;
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Tsw = switch_inf[iswitch].Tdel;
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if (switch_inf[iswitch].buffered) {
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rr_indexed_data[cost_index].T_linear = Tsw + Rsw * Cnode
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+ 0.5 * Rnode * Cnode;
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rr_indexed_data[cost_index].T_quadratic = 0.;
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rr_indexed_data[cost_index].C_load = 0.;
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} else { /* Pass transistor */
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rr_indexed_data[cost_index].C_load = Cnode;
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/* See Dec. 23, 1997 notes for deriviation of formulae. */
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rr_indexed_data[cost_index].T_linear = Tsw + 0.5 * Rsw * Cnode;
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rr_indexed_data[cost_index].T_quadratic = (Rsw + Rnode) * 0.5
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* Cnode;
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/* mrFPGA: Xifan TANG */
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if (is_mrFPGA && is_wire_buffer) {
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rr_indexed_data[cost_index].T_linear += wire_buffer_inf.R * Cnode + wire_buffer_inf.C * (Rnode + Rsw)
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+ sqrt(rr_indexed_data[cost_index].T_quadratic * (wire_buffer_inf.Tdel
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+ wire_buffer_inf.R * wire_buffer_inf.C));
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rr_indexed_data[cost_index].T_quadratic = 0.;
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}
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/* end */
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}
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}
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}
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free(num_nodes_of_index);
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free(C_total);
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free(R_total);
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}
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