tangxifan a20f6eaf06 [Engine] Fixed a few bugs		2022-04-10 21:29:38 +08:00
..
annotation	[Engine] Fixed a few bugs	2022-04-10 21:29:38 +08:00
base	[Engine] Now GSB output file contains segments name and pin name in SB module	2022-04-10 21:22:30 +08:00
fabric	[Engine] Now global port can be connected partial pins of a tile port	2022-03-20 11:36:03 +08:00
fpga_bitstream	[FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats	2022-03-29 19:41:15 +08:00
fpga_sdc	[FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands	2022-01-25 15:51:28 -08:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports	2022-03-16 20:51:37 +08:00
mux_lib	[Engine] Support WLR port in OpenFPGA architecture file and fabric generator	2021-09-20 16:05:36 -07:00
repack	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[FPGA-Verilog] Now output atom block name removal has a dedicated function	2022-02-18 14:30:46 -08:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00