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behavioral_verilog_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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bitstream_setting_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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configuration_chain_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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custom_fabric_netlist_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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duplicated_grid_pin_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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example_without_ace_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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fast_configuration_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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fix_device_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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fix_device_global_tile_clock_bitstream_setting_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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fix_device_global_tile_clock_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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fix_device_route_chan_width_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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fix_heterogeneous_device_example_script.openfpga
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[test] disable clustering-routing result sync-up when calling vpr in example scripts
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2022-09-19 20:52:04 -07:00 |
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fix_pins_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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flatten_routing_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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full_testbench_bus_group_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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full_testbench_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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full_testbench_example_without_ace_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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full_testbench_without_self_checking_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_bitstream_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_bitstream_fix_device_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_bitstream_global_tile_multiclock_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_fabric_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_fabric_key_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_secure_fabric_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_secure_fabric_from_key_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_spice_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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generate_testbench_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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global_tile_clock_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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global_tile_clock_full_testbench_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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global_tile_multiclock_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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ignore_global_nets_on_pins_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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implicit_verilog_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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iverilog_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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iwls_benchmark_example_script.openfpga
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[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
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2022-09-20 12:08:24 -07:00 |
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load_external_arch_bitstream_example_script.openfpga
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[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
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2022-09-20 14:14:18 -07:00 |
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mcnc_example_script.openfpga
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[script] turn off the pb_pin_fix_up in vpr run for mcnc and vtr benchmarks
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2022-08-27 20:04:29 -07:00 |
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no_time_stamp_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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pin_constrain_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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preconfig_fabric_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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preconfigured_testbench_bus_group_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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preconfigured_testbench_no_time_stamp_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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preconfigured_testbench_relative_path_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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preconfigured_testbench_without_self_checking_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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quicklogic_flow_example_script.openfpga
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[test] now use a fixed routing channel width for quicklogic tests
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2022-09-20 12:25:40 -07:00 |
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rename_scripts.sh
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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report_bitstream_distribution_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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sdc_time_unit_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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skywater_tapeout_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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verilog_default_net_type_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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vtr_benchmark_example_script.openfpga
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[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
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2022-09-20 12:08:24 -07:00 |
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write_full_testbench_dont_care_bits_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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write_full_testbench_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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write_full_testbench_relative_path_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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write_gsb_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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write_io_mapping_example_script.openfpga
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
