508 lines
21 KiB
C
508 lines
21 KiB
C
/***********************************/
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/* Synthesizable Verilog Dumping */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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#include <vector>
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/* Include vpr structs*/
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#include "vtr_geometry.h"
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "vpr_utils.h"
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#include "path_delay.h"
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#include "stats.h"
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#include "route_common.h"
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/* Include FPGA-SPICE utils */
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#include "read_xml_spice_util.h"
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#include "linkedlist.h"
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#include "fpga_x2p_types.h"
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_pbtypes_utils.h"
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#include "fpga_x2p_backannotate_utils.h"
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#include "fpga_x2p_globals.h"
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#include "fpga_bitstream.h"
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#include "module_manager.h"
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#include "mux_library.h"
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#include "mux_library_builder.h"
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/* Include SynVerilog headers */
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#include "verilog_global.h"
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#include "verilog_utils.h"
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#include "verilog_submodules.h"
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#include "verilog_decoder.h"
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#include "verilog_decoders.h"
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#include "verilog_pbtypes.h"
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#include "verilog_grid.h"
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#include "verilog_routing.h"
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#include "verilog_top_module.h"
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#include "verilog_compact_netlist.h"
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#include "verilog_top_testbench.h"
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#include "verilog_autocheck_top_testbench.h"
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#include "verilog_formal_random_top_testbench.h"
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#include "verilog_verification_top_netlist.h"
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#include "verilog_modelsim_autodeck.h"
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#include "verilog_report_timing.h"
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#include "verilog_sdc.h"
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#include "verilog_formality_autodeck.h"
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#include "verilog_sdc_pb_types.h"
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#include "verilog_include_netlists.h"
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#include "verilog_api.h"
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/***** Subroutines *****/
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/* Alloc array that records Configuration bits for :
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* (1) Switch blocks
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* (2) Connection boxes
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* TODO: Can be improved in alloc strategy to be more memory efficient!
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*/
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static
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void alloc_global_routing_conf_bits() {
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int i;
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/* Alloc array for Switch blocks */
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num_conf_bits_sb = (int**)my_malloc((nx+1)*sizeof(int*));
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for (i = 0; i < (nx + 1); i++) {
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num_conf_bits_sb[i] = (int*)my_calloc((ny+1), sizeof(int));
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}
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/* Alloc array for Connection blocks */
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num_conf_bits_cbx = (int**)my_malloc((nx+1)*sizeof(int*));
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for (i = 0; i < (nx + 1); i++) {
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num_conf_bits_cbx[i] = (int*)my_calloc((ny+1), sizeof(int));
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}
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num_conf_bits_cby = (int**)my_malloc((nx+1)*sizeof(int*));
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for (i = 0; i < (nx + 1); i++) {
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num_conf_bits_cby[i] = (int*)my_calloc((ny+1), sizeof(int));
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}
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return;
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}
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static
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void free_global_routing_conf_bits() {
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int i;
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/* Free array for Switch blocks */
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for (i = 0; i < (nx + 1); i++) {
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my_free(num_conf_bits_sb[i]);
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}
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my_free(num_conf_bits_sb);
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/* Free array for Connection box */
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for (i = 0; i < (nx + 1); i++) {
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my_free(num_conf_bits_cbx[i]);
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}
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my_free(num_conf_bits_cbx);
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for (i = 0; i < (nx + 1); i++) {
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my_free(num_conf_bits_cby[i]);
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}
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my_free(num_conf_bits_cby);
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return;
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}
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/* Top-level function*/
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void vpr_fpga_verilog(ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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t_vpr_setup vpr_setup,
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t_arch Arch,
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char* circuit_name) {
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/* Timer */
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clock_t t_start;
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clock_t t_end;
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float run_time_sec;
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int num_clocks = Arch.spice->spice_params.stimulate_params.num_clocks;
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/* int vpr_crit_path_delay = Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay; */
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/* Directory paths */
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char* verilog_dir_formatted = NULL;
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char* src_dir_path = NULL;
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char* submodule_dir_path= NULL;
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char* lb_dir_path = NULL;
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char* rr_dir_path = NULL;
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char* tcl_dir_path = NULL;
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char* sdc_dir_path = NULL;
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char* msim_dir_path = NULL;
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char* fm_dir_path = NULL;
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char* top_netlist_file = NULL;
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char* top_netlist_path = NULL;
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char* top_testbench_file_name = NULL;
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char* top_testbench_file_path = NULL;
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char* blif_testbench_file_name = NULL;
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char* blif_testbench_file_path = NULL;
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char* bitstream_file_name = NULL;
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char* bitstream_file_path = NULL;
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char* formal_verification_top_netlist_file_name = NULL;
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char* formal_verification_top_netlist_file_path = NULL;
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char* autocheck_top_testbench_file_name = NULL;
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char* autocheck_top_testbench_file_path = NULL;
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char* random_top_testbench_file_name = NULL;
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char* random_top_testbench_file_path = NULL;
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char* chomped_parent_dir = NULL;
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char* chomped_circuit_name = NULL;
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t_sram_orgz_info* sram_verilog_orgz_info = NULL;
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/* 0. basic units: inverter, buffers and pass-gate logics, */
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/* Check if the routing architecture we support*/
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if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) {
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vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable Verilog dumping only support uni-directional routing architecture!\n");
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exit(1);
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}
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/* We don't support mrFPGA */
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#ifdef MRFPGA_H
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if (is_mrFPGA) {
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vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable verilog dumping do not support mrFPGA!\n");
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exit(1);
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}
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#endif
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assert ( TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog);
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/* VerilogGenerator formally starts*/
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vpr_printf(TIO_MESSAGE_INFO, "\nFPGA synthesizable verilog generator starts...\n");
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/* Start time count */
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t_start = clock();
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/* Format the directory paths */
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split_path_prog_name(circuit_name, '/', &chomped_parent_dir, &chomped_circuit_name);
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if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir) {
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verilog_dir_formatted = format_dir_path(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir);
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} else {
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verilog_dir_formatted = format_dir_path(my_strcat(format_dir_path(chomped_parent_dir), default_verilog_dir_name));
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}
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/* SRC directory */
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src_dir_path = format_dir_path(my_strcat(verilog_dir_formatted, default_src_dir_name));
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/* lb directory */
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lb_dir_path = my_strcat(src_dir_path, default_lb_dir_name);
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/* routing resources directory */
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rr_dir_path = my_strcat(src_dir_path, default_rr_dir_name);
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/* submodule_dir_path */
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submodule_dir_path = my_strcat(src_dir_path, default_submodule_dir_name);
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/* SDC_dir_path */
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sdc_dir_path = my_strcat(verilog_dir_formatted, default_sdc_dir_name);
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/* tcl_dir_path */
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tcl_dir_path = my_strcat(verilog_dir_formatted, default_tcl_dir_name);
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/* msim_dir_path */
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msim_dir_path = my_strcat(verilog_dir_formatted, default_msim_dir_name);
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/* fm_dir_path */
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fm_dir_path = my_strcat(verilog_dir_formatted, default_snpsfm_dir_name);
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/* Top netlists dir_path */
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top_netlist_file = my_strcat(chomped_circuit_name, verilog_top_postfix);
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top_netlist_path = my_strcat(src_dir_path, top_netlist_file);
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/* Report timing directory */
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if (NULL == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.report_timing_path) {
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.report_timing_path = my_strcat(verilog_dir_formatted, default_report_timing_rpt_dir_name);
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}
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/* Create directories */
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create_dir_path(verilog_dir_formatted);
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create_dir_path(src_dir_path);
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create_dir_path(lb_dir_path);
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create_dir_path(rr_dir_path);
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create_dir_path(sdc_dir_path);
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create_dir_path(tcl_dir_path);
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create_dir_path(fm_dir_path);
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create_dir_path(msim_dir_path);
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create_dir_path(submodule_dir_path);
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/* assign the global variable of SRAM model */
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assert(NULL != Arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/
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sram_verilog_model = Arch.sram_inf.verilog_sram_inf_orgz->spice_model;
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/* initialize the SRAM organization information struct */
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sram_verilog_orgz_info = alloc_one_sram_orgz_info();
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init_sram_orgz_info(sram_verilog_orgz_info, Arch.sram_inf.verilog_sram_inf_orgz->type, sram_verilog_model, nx + 2, ny + 2);
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/* Check all the SRAM port is using the correct SRAM SPICE MODEL */
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config_spice_models_sram_port_spice_model(Arch.spice->num_spice_model,
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Arch.spice->spice_models,
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Arch.sram_inf.verilog_sram_inf_orgz->spice_model);
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config_circuit_models_sram_port_to_default_sram_model(Arch.spice->circuit_lib, Arch.sram_inf.verilog_sram_inf_orgz->circuit_model);
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/* Assign global variables of input and output pads */
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iopad_verilog_model = find_iopad_spice_model(Arch.spice->num_spice_model, Arch.spice->spice_models);
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assert(NULL != iopad_verilog_model);
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/* zero the counter of each spice_model */
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zero_spice_models_cnt(Arch.spice->num_spice_model, Arch.spice->spice_models);
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/* Initialize the user-defined verilog netlists to be included */
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init_list_include_verilog_netlists(Arch.spice);
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/* Initial global variables about configuration bits */
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alloc_global_routing_conf_bits();
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/* Initialize the number of configuration bits of all the grids */
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vpr_printf(TIO_MESSAGE_INFO, "Count the number of configuration bits, IO pads in each logic block...\n");
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/* init_grids_num_conf_bits(sram_verilog_orgz_type); */
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//init_grids_num_conf_bits(sram_verilog_orgz_info);
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init_pb_types_num_conf_bits(sram_verilog_orgz_info);
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//init_grids_num_iopads();
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init_pb_types_num_iopads();
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/* init_grids_num_mode_bits(); */
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dump_verilog_defines_preproc(src_dir_path,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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dump_verilog_simulation_preproc(src_dir_path,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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/* Generate primitive Verilog modules, which are corner stones of FPGA fabric
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* Note that this function MUST be called before Verilog generation of
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* core logic (i.e., logic blocks and routing resources) !!!
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* This is because that this function will add the primitive Verilog modules to
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* the module manager.
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* Without the modules in the module manager, core logic generation is not possible!!!
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*/
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dump_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path, submodule_dir_path,
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Arch, &vpr_setup.RoutingArch,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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/* Dump routing resources: switch blocks, connection blocks and channel tracks */
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print_verilog_routing_resources(module_manager, mux_lib, sram_verilog_orgz_info,
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src_dir_path, rr_dir_path, Arch, vpr_setup.RoutingArch,
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num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data,
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vpr_setup.FPGA_SPICE_Opts);
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/* Dump logic blocks
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* Branches to go:
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* 1. a compact output
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* 2. a full-size output
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*/
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print_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path,
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lb_dir_path, Arch,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
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print_verilog_grids(module_manager, Arch.spice->circuit_lib, mux_lib,
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sram_verilog_orgz_info,
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std::string(src_dir_path), std::string(lb_dir_path),
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TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
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/* Generate the Verilog module of the configuration peripheral protocol
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* which loads bitstream to FPGA fabric
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* TODO: generate the BL/WL decoders!!!!
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*
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* IMPORTANT: this function should be called after Verilog generation of
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* core logic (i.e., logic blocks and routing resources) !!!
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* This is due to the configuration protocol requires the total
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* number of memory cells across the FPGA fabric
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*/
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print_verilog_config_peripherals(module_manager, sram_verilog_orgz_info, std::string(src_dir_path), std::string(submodule_dir_path));
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/* TODO: This is the old function, which will be deprecated when refactoring is done */
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dump_verilog_config_peripherals(sram_verilog_orgz_info, src_dir_path, submodule_dir_path);
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/* Print top-level Verilog module */
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vtr::Point<size_t> device_size(nx + 2, ny + 2);
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std::vector<std::vector<t_grid_tile>> grids;
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/* Organize a vector (matrix) of grids to feed the top-level module generation */
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grids.resize(device_size.x());
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for (size_t ix = 0; ix < device_size.x(); ++ix) {
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grids[ix].resize(device_size.y());
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for (size_t iy = 0; iy < device_size.y(); ++iy) {
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grids[ix][iy] = grid[ix][iy];
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}
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}
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/* Organize a vector (matrix) of clb2clb directs to feed the top-level module generation */
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std::vector<t_clb_to_clb_directs> clb2clb_directs;
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for (int i = 0; i < num_clb2clb_directs; ++i) {
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clb2clb_directs.push_back(clb2clb_direct[i]);
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}
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print_verilog_top_module(module_manager, Arch.spice->circuit_lib,
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device_size, grids, device_rr_gsb,
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clb2clb_directs,
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sram_verilog_orgz_info,
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std::string(vpr_setup.FileNameOpts.ArchFile),
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std::string(src_dir_path),
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TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy,
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TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
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/* TODO: This is the old function, which will be deprecated when refactoring is done */
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dump_compact_verilog_top_netlist(sram_verilog_orgz_info, chomped_circuit_name,
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top_netlist_path, src_dir_path, submodule_dir_path, lb_dir_path, rr_dir_path,
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num_rr_nodes, rr_node, rr_node_indices,
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num_clocks,
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vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy,
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*(Arch.spice), vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
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/* Dump SDC constraints */
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/* Output SDC to contrain the P&R flow
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*/
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr) {
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verilog_generate_sdc_pnr(sram_verilog_orgz_info, sdc_dir_path,
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Arch, &vpr_setup.RoutingArch,
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num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data,
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nx, ny, device_rr_gsb,
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vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
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}
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/* dump verilog testbench only for input blif */
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_input_blif_testbench) {
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blif_testbench_file_name = my_strcat(chomped_circuit_name, blif_testbench_verilog_file_postfix);
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blif_testbench_file_path = my_strcat(src_dir_path, blif_testbench_file_name);
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dump_verilog_input_blif_testbench(chomped_circuit_name, blif_testbench_file_path, src_dir_path,
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*(Arch.spice));
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/* Free */
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my_free(blif_testbench_file_name);
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my_free(blif_testbench_file_path);
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}
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/* Free sram_orgz_info:
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* Free the allocated sram_orgz_info before, we start bitstream generation !
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*/
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free_sram_orgz_info(sram_verilog_orgz_info,
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sram_verilog_orgz_info->type);
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/* Force enable bitstream generator when we need to output Verilog top testbench*/
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if ((TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream)
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|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench)
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|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench)
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|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist)) {
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vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream = TRUE;
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}
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/* Generate bitstream if required, and also Dump bitstream file */
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if (TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) {
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bitstream_file_name = my_strcat(chomped_circuit_name, fpga_spice_bitstream_output_file_postfix);
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bitstream_file_path = my_strcat(src_dir_path, bitstream_file_name);
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/* Run bitstream generation */
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vpr_fpga_generate_bitstream(vpr_setup, Arch, circuit_name, bitstream_file_path, &sram_verilog_orgz_info);
|
|
my_free(bitstream_file_name);
|
|
my_free(bitstream_file_path);
|
|
}
|
|
|
|
/* dump verilog testbench only for top-level: ONLY valid when bitstream is generated! */
|
|
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench) {
|
|
top_testbench_file_name = my_strcat(chomped_circuit_name, top_testbench_verilog_file_postfix);
|
|
top_testbench_file_path = my_strcat(src_dir_path, top_testbench_file_name);
|
|
dump_verilog_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, top_testbench_file_path,
|
|
src_dir_path, *(Arch.spice));
|
|
/* Free */
|
|
my_free(top_testbench_file_name);
|
|
my_free(top_testbench_file_path);
|
|
}
|
|
|
|
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) {
|
|
formal_verification_top_netlist_file_name = my_strcat(chomped_circuit_name, formal_verification_verilog_file_postfix);
|
|
formal_verification_top_netlist_file_path = my_strcat(src_dir_path, formal_verification_top_netlist_file_name);
|
|
dump_verilog_formal_verification_top_netlist(sram_verilog_orgz_info, chomped_circuit_name,
|
|
formal_verification_top_netlist_file_path, src_dir_path);
|
|
/* Output script for formality */
|
|
write_formality_script(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts,
|
|
fm_dir_path,
|
|
src_dir_path,
|
|
chomped_circuit_name,
|
|
*(Arch.spice));
|
|
random_top_testbench_file_name = my_strcat(chomped_circuit_name, random_top_testbench_verilog_file_postfix);
|
|
random_top_testbench_file_path = my_strcat(src_dir_path, random_top_testbench_file_name);
|
|
dump_verilog_random_top_testbench(sram_verilog_orgz_info, chomped_circuit_name,
|
|
random_top_testbench_file_path, src_dir_path,
|
|
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
|
|
/* Free */
|
|
my_free(formal_verification_top_netlist_file_name);
|
|
my_free(formal_verification_top_netlist_file_path);
|
|
}
|
|
|
|
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) {
|
|
autocheck_top_testbench_file_name = my_strcat(chomped_circuit_name, autocheck_top_testbench_verilog_file_postfix);
|
|
autocheck_top_testbench_file_path = my_strcat(src_dir_path, autocheck_top_testbench_file_name);
|
|
dump_verilog_autocheck_top_testbench(sram_verilog_orgz_info, chomped_circuit_name,
|
|
autocheck_top_testbench_file_path, src_dir_path,
|
|
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
|
|
/* Free */
|
|
my_free(autocheck_top_testbench_file_name);
|
|
my_free(autocheck_top_testbench_file_path);
|
|
}
|
|
|
|
/* Output Modelsim Autodeck scripts */
|
|
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_modelsim_autodeck) {
|
|
dump_verilog_modelsim_autodeck(sram_verilog_orgz_info,
|
|
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts,
|
|
*(Arch.spice),
|
|
Arch.spice->spice_params.meas_params.sim_num_clock_cycle,
|
|
msim_dir_path,
|
|
chomped_circuit_name,
|
|
src_dir_path);
|
|
}
|
|
|
|
/* Output SDC to contrain the mapped FPGA in timing-analysis purpose
|
|
*/
|
|
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_analysis) {
|
|
verilog_generate_sdc_analysis(sram_verilog_orgz_info, sdc_dir_path,
|
|
Arch,
|
|
num_rr_nodes, rr_node, rr_node_indices,
|
|
nx, ny, grid, block, device_rr_gsb,
|
|
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
|
|
}
|
|
/* Output routing report_timing script :
|
|
*/
|
|
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_report_timing_tcl) {
|
|
verilog_generate_report_timing(sram_verilog_orgz_info, tcl_dir_path,
|
|
Arch, &vpr_setup.RoutingArch,
|
|
num_rr_nodes, rr_node, rr_node_indices,
|
|
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts,
|
|
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
|
|
}
|
|
|
|
if ((TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream)
|
|
|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench)
|
|
|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench)
|
|
|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist)) {
|
|
/* Free sram_orgz_info:
|
|
* Free the allocated sram_orgz_info before, we start bitstream generation !
|
|
*/
|
|
free_sram_orgz_info(sram_verilog_orgz_info,
|
|
sram_verilog_orgz_info->type);
|
|
}
|
|
|
|
write_include_netlists(src_dir_path,
|
|
chomped_circuit_name,
|
|
*(Arch.spice) );
|
|
|
|
vpr_printf(TIO_MESSAGE_INFO, "Outputted %lu Verilog modules in total.\n", module_manager.num_modules());
|
|
|
|
/* End time count */
|
|
t_end = clock();
|
|
|
|
run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
|
|
vpr_printf(TIO_MESSAGE_INFO, "Synthesizable verilog dumping took %g seconds\n", run_time_sec);
|
|
|
|
/* Free global array */
|
|
free_global_routing_conf_bits();
|
|
|
|
/* Free */
|
|
my_free(verilog_dir_formatted);
|
|
my_free(src_dir_path);
|
|
my_free(lb_dir_path);
|
|
my_free(rr_dir_path);
|
|
my_free(msim_dir_path);
|
|
my_free(fm_dir_path);
|
|
my_free(sdc_dir_path);
|
|
my_free(tcl_dir_path);
|
|
my_free(top_netlist_file);
|
|
my_free(top_netlist_path);
|
|
my_free(submodule_dir_path);
|
|
|
|
return;
|
|
}
|