ganeshgore 3b6cd885f3 BugFix: Fixed yosys_vpr with openFPGA_Shell		2020-07-22 11:57:04 -06:00
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OpenFPGAShellScripts	add bitstream generation only test case to CI	2020-07-02 16:31:22 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	update arch to support reset signal for SRAm	2020-06-11 19:31:14 -06:00
benchmarks	start using counter benchmark in regression tests	2020-06-11 19:31:15 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	fabric key can now accept instance name only; decoders are no longer part of the key	2020-07-06 16:42:33 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	use configuration chain in the k4k4 test case to speed up CI	2020-07-15 11:56:11 -06:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	BugFix: Fixed yosys_vpr with openFPGA_Shell	2020-07-22 11:57:04 -06:00
tasks	add fast configuration chain test case	2020-07-15 11:56:47 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	rename arch directory to be clear for its usage	2020-07-04 19:13:28 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00