231 lines
8.0 KiB
C
231 lines
8.0 KiB
C
/***********************************/
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/* Synthesizable Verilog Dumping */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "vpr_utils.h"
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#include "path_delay.h"
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#include "stats.h"
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/* Include FPGA-SPICE utils */
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#include "linkedlist.h"
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#include "fpga_spice_utils.h"
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#include "spice_mux.h"
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#include "fpga_spice_globals.h"
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/* Include verilog utils */
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#include "verilog_global.h"
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#include "verilog_utils.h"
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/***** Subroutines *****/
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void determine_verilog_blwl_decoder_size(INP t_sram_orgz_info* cur_sram_verilog_orgz_info,
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OUTP int* num_array_bl, OUTP int* num_array_wl,
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OUTP int* bl_decoder_size, OUTP int* wl_decoder_size) {
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t_spice_model* mem_model = NULL;
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int num_mem_bit;
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int num_reserved_bl, num_reserved_wl;
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/* Check */
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assert(SPICE_SRAM_MEMORY_BANK == sram_verilog_orgz_info->type);
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num_mem_bit = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info);
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get_sram_orgz_info_num_blwl(sram_verilog_orgz_info, num_array_bl, num_array_wl);
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get_sram_orgz_info_reserved_blwl(sram_verilog_orgz_info, &num_reserved_bl, &num_reserved_wl);
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/* Sizes of decodes depend on the Memory technology */
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get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model);
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switch (mem_model->design_tech) {
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/* CMOS SRAM*/
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case SPICE_MODEL_DESIGN_CMOS:
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/* SRAMs can efficiently share BLs and WLs,
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* Actual number of BLs and WLs will be sqrt(num_bls) and sqrt(num_wls)
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*/
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assert(0 == num_reserved_bl);
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assert(0 == num_reserved_wl);
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(*num_array_bl) = ceil(sqrt(*num_array_bl));
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(*num_array_wl) = ceil(sqrt(*num_array_wl));
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(*bl_decoder_size) = determine_decoder_size(*num_array_bl);
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(*wl_decoder_size) = determine_decoder_size(*num_array_wl);
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break;
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/* RRAM */
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case SPICE_MODEL_DESIGN_RRAM:
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/* Currently we do not have more efficient way to share the BLs and WLs as CMOS SRAMs */
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(*bl_decoder_size) = determine_decoder_size(*num_array_bl);
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(*wl_decoder_size) = determine_decoder_size(*num_array_wl);
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology [CMOS|RRAM] for memory technology!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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return;
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}
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void dump_verilog_decoder(char* submodule_dir) {
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int num_array_bl, num_array_wl;
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int bl_decoder_size, wl_decoder_size;
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FILE* fp = NULL;
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t_spice_model* mem_model = NULL;
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boolean bl_inverted = FALSE;
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boolean wl_inverted = FALSE;
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char* verilog_name = my_strcat(submodule_dir, decoders_verilog_file_name);
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/* Print the muxes netlist*/
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fp = fopen(verilog_name, "w");
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create decoder SPICE netlist %s",__FILE__, __LINE__, verilog_name);
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exit(1);
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}
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/* Check */
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assert(SPICE_SRAM_MEMORY_BANK == sram_verilog_orgz_info->type);
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/* Get number of BLs,WLs and decoder sizes */
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determine_verilog_blwl_decoder_size(sram_verilog_orgz_info,
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&num_array_bl, &num_array_wl,
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&bl_decoder_size, &wl_decoder_size);
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/* Generate file header*/
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vpr_printf(TIO_MESSAGE_INFO, "Writing Decoder verilog netlist...\n");
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/* Generate the descriptions*/
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dump_verilog_file_header(fp, " Verilog Decoders");
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/* Different design technology requires different BL decoder logic */
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get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model);
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/* Find if we need an inversion of the BL */
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check_mem_model_blwl_inverted(mem_model, SPICE_MODEL_PORT_BL, &bl_inverted);
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check_mem_model_blwl_inverted(mem_model, SPICE_MODEL_PORT_WL, &wl_inverted);
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switch (mem_model->design_tech) {
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case SPICE_MODEL_DESIGN_CMOS: /* CMOS SRAM*/
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/* SRAM technology requires its BL decoder has an additional input called data_in
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* only the selected BL will be set to the value of data_in, other BLs will be in high-resistance state
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*/
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/* Start the BL decoder module definition */
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fprintf(fp, "//----- BL Decoder convert %d bits to binary %d bits -----\n",
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bl_decoder_size, num_array_bl);
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fprintf(fp, "module bl_decoder%dto%d (\n",
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bl_decoder_size, num_array_bl);
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fprintf(fp, "input wire enable,\n");
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fprintf(fp, "input wire [%d:0] addr_in,\n",
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bl_decoder_size - 1);
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fprintf(fp, "input wire data_in,\n");
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fprintf(fp, "output reg [0:%d] addr_out\n",
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num_array_bl - 1);
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fprintf(fp, ");\n");
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/* Wee need to know the default value of bl port and wl port */
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/* Internal logics */
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fprintf(fp, "always@(addr_out,addr_in,enable, data_in)\n");
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fprintf(fp, "begin\n");
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fprintf(fp, "\taddr_out = %d'bz;\n", num_array_bl);
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fprintf(fp, "\tif (1'b1 == enable) begin\n");
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fprintf(fp, "\t\taddr_out[addr_in] = data_in;\n");
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fprintf(fp, "\tend\n");
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fprintf(fp, "end\n");
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fprintf(fp, "endmodule\n");
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break;
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case SPICE_MODEL_DESIGN_RRAM: /* RRAM */
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/* For RRAM technology, BL decoder should be same as the WL decoder */
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/* Start the BL decoder module definition */
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fprintf(fp, "//----- BL Decoder convert %d bits to binary %d bits -----\n",
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bl_decoder_size, num_array_bl);
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fprintf(fp, "module bl_decoder%dto%d (\n",
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bl_decoder_size, num_array_bl);
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fprintf(fp, "input wire enable,\n");
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fprintf(fp, "input wire [%d:0] addr_in,\n",
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bl_decoder_size-1);
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fprintf(fp, "output reg [0:%d] addr_out\n",
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num_array_bl-1);
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fprintf(fp, ");\n");
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/* Internal logics */
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fprintf(fp, "always@(addr_out,addr_in,enable)\n");
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fprintf(fp, "begin\n");
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if (TRUE == bl_inverted) {
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fprintf(fp, "\taddr_out = %d'b1;\n", num_array_bl);
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} else {
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assert (FALSE == bl_inverted);
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fprintf(fp, "\taddr_out = %d'b0;\n", num_array_bl);
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}
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fprintf(fp, "\tif (1'b1 == enable) begin\n");
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if (TRUE == bl_inverted) {
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fprintf(fp, "\t\taddr_out[addr_in] = 1'b0;\n");
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} else {
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assert (FALSE == bl_inverted);
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fprintf(fp, "\t\taddr_out[addr_in] = 1'b1;\n");
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}
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fprintf(fp, "\tend\n");
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fprintf(fp, "end\n");
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fprintf(fp, "endmodule\n");
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology [CMOS|RRAM] for memory technology!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* WL decoder logic is the same whatever SRAM or RRAM technology is considered */
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/* Start the WL module definition */
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fprintf(fp, "//----- WL Decoder convert %d bits to binary %d bits -----\n",
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wl_decoder_size, num_array_wl);
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fprintf(fp, "module wl_decoder%dto%d (\n",
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wl_decoder_size, num_array_wl);
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fprintf(fp, "input wire enable,\n");
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fprintf(fp, "input wire [%d:0] addr_in,\n",
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wl_decoder_size-1);
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fprintf(fp, "output reg [0:%d] addr_out\n",
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num_array_bl-1);
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fprintf(fp, ");\n");
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/* Internal logics */
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fprintf(fp, "always@(addr_out,addr_in,enable)\n");
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fprintf(fp, "begin\n");
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if (TRUE == wl_inverted) {
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fprintf(fp, "\taddr_out = %d'b1;\n", num_array_wl);
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} else {
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assert (FALSE == wl_inverted);
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fprintf(fp, "\taddr_out = %d'b0;\n", num_array_wl);
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}
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fprintf(fp, "\tif (1'b1 == enable) begin\n");
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if (TRUE == wl_inverted) {
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fprintf(fp, "\t\taddr_out[addr_in] = 1'b0;\n");
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} else {
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assert (FALSE == wl_inverted);
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fprintf(fp, "\t\taddr_out[addr_in] = 1'b1;\n");
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}
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fprintf(fp, "\tend\n");
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fprintf(fp, "end\n");
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fprintf(fp, "endmodule\n");
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/* Close the file*/
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fclose(fp);
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/* Add fname to the linked list */
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submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name);
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return;
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}
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