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OpenFPGA
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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_spice
History
AurelienUoU 21dc8a006f Change simulator script generation (waves) 2018-12-14 14:40:04 -07:00
..
base update blif reader to identify clock signals 2018-12-10 13:28:44 -07:00
clb_pin_remap rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
spice fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
verilog Change simulator script generation (waves) 2018-12-14 14:40:04 -07:00