394 lines
15 KiB
C
394 lines
15 KiB
C
/***********************************/
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/* SPICE Modeling for VPR */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "vpr_utils.h"
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#include "path_delay.h"
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#include "stats.h"
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/* Include spice support headers*/
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#include "read_xml_spice_util.h"
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#include "linkedlist.h"
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#include "fpga_spice_utils.h"
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#include "fpga_spice_backannotate_utils.h"
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#include "fpga_spice_globals.h"
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#include "fpga_spice_bitstream.h"
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/* Include SPICE generator headers */
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#include "spice_globals.h"
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#include "spice_subckt.h"
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#include "spice_pbtypes.h"
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#include "spice_heads.h"
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#include "spice_lut.h"
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#include "spice_top_netlist.h"
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#include "spice_mux_testbench.h"
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#include "spice_grid_testbench.h"
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#include "spice_lut_testbench.h"
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#include "spice_routing_testbench.h"
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#include "spice_hardlogic_testbench.h"
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#include "spice_run_scripts.h"
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/* For mrFPGA */
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#ifdef MRFPGA_H
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#include "mrfpga_globals.h"
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#endif
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/* RUN HSPICE Shell Script Name */
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static char* default_spice_dir_path = "spice_netlists/";
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static char* spice_top_tb_dir_name = "top_tb/";
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static char* spice_grid_tb_dir_name = "grid_tb/";
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static char* spice_pb_mux_tb_dir_name = "pb_mux_tb/";
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static char* spice_cb_mux_tb_dir_name = "cb_mux_tb/";
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static char* spice_sb_mux_tb_dir_name = "sb_mux_tb/";
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static char* spice_cb_tb_dir_name = "cb_tb/";
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static char* spice_sb_tb_dir_name = "sb_tb/";
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static char* spice_lut_tb_dir_name = "lut_tb/";
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static char* spice_hardlogic_tb_dir_name = "hardlogic_tb/";
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/***** Subroutines Declarations *****/
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static
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void init_list_include_netlists(t_spice* spice);
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static
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void free_spice_tb_llist();
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/***** Subroutines *****/
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static
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void init_list_include_netlists(t_spice* spice) {
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int i, j, cur;
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int to_include = 0;
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int num_to_include = 0;
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/* Initialize */
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for (i = 0; i < spice->num_include_netlist; i++) {
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FreeSpiceModelNetlist(&(spice->include_netlists[i]));
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}
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my_free(spice->include_netlists);
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spice->include_netlists = NULL;
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spice->num_include_netlist = 0;
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/* Generate include netlist list */
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vpr_printf(TIO_MESSAGE_INFO, "Listing SPICE Netlist Names to be included...\n");
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for (i = 0; i < spice->num_spice_model; i++) {
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if (NULL != spice->spice_models[i].model_netlist) {
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/* Check if this netlist name has already existed in the list */
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to_include = 1;
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for (j = 0; j < i; j++) {
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if (NULL == spice->spice_models[j].model_netlist) {
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continue;
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}
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if (0 == strcmp(spice->spice_models[j].model_netlist, spice->spice_models[i].model_netlist)) {
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to_include = 0;
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break;
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}
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}
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/* Increamental */
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if (1 == to_include) {
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num_to_include++;
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}
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}
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}
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/* realloc */
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spice->include_netlists = (t_spice_model_netlist*)my_realloc(spice->include_netlists,
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sizeof(t_spice_model_netlist)*(num_to_include + spice->num_include_netlist));
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/* Fill the new included netlists */
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cur = spice->num_include_netlist;
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for (i = 0; i < spice->num_spice_model; i++) {
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if (NULL != spice->spice_models[i].model_netlist) {
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/* Check if this netlist name has already existed in the list */
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to_include = 1;
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for (j = 0; j < i; j++) {
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if (NULL == spice->spice_models[j].model_netlist) {
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continue;
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}
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if (0 == strcmp(spice->spice_models[j].model_netlist, spice->spice_models[i].model_netlist)) {
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to_include = 0;
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break;
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}
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}
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/* Increamental */
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if (1 == to_include) {
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spice->include_netlists[cur].path = my_strdup(spice->spice_models[i].model_netlist);
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spice->include_netlists[cur].included = 0;
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vpr_printf(TIO_MESSAGE_INFO, "[%d] %s\n", cur+1, spice->include_netlists[cur].path);
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cur++;
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}
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}
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}
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/* Check */
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assert(cur == (num_to_include + spice->num_include_netlist));
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/* Update */
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spice->num_include_netlist += num_to_include;
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return;
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}
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static
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void free_spice_tb_llist() {
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t_llist* temp = tb_head;
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while (temp) {
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my_free(((t_spicetb_info*)(temp->dptr))->tb_name);
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my_free(temp->dptr);
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temp->dptr = NULL;
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temp = temp->next;
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}
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free_llist(tb_head);
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return;
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}
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/***** Main Function *****/
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void vpr_print_spice_netlists(t_vpr_setup vpr_setup,
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t_arch Arch,
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char* circuit_name) {
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clock_t t_start;
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clock_t t_end;
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float run_time_sec;
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int num_clocks = Arch.spice->spice_params.stimulate_params.num_clocks;
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int vpr_crit_path_delay = Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay;
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char* spice_dir_formatted = NULL;
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char* include_dir_path = NULL;
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char* subckt_dir_path = NULL;
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char* top_netlist_path = NULL;
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char* include_dir_name = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.include_dir;
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char* subckt_dir_name = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.subckt_dir;
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char* chomped_circuit_name = NULL;
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char* chomped_spice_dir = NULL;
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char* top_testbench_dir_path = NULL;
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char* pb_mux_testbench_dir_path = NULL;
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char* cb_mux_testbench_dir_path = NULL;
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char* sb_mux_testbench_dir_path = NULL;
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char* cb_testbench_dir_path = NULL;
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char* sb_testbench_dir_path = NULL;
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char* grid_testbench_dir_path = NULL;
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char* lut_testbench_dir_path = NULL;
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char* hardlogic_testbench_dir_path = NULL;
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char* top_testbench_file = NULL;
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char* bitstream_file_name = NULL;
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char* bitstream_file_path = NULL;
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/* Check if the routing architecture we support*/
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if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) {
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vpr_printf(TIO_MESSAGE_ERROR, "FPGA SPICE netlists only support uni-directional routing architecture!\n");
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exit(1);
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}
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/* We don't support mrFPGA */
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#ifdef MRFPGA_H
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if (is_mrFPGA) {
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vpr_printf(TIO_MESSAGE_ERROR, "FPGA SPICE netlists do not support mrFPGA!\n");
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exit(1);
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}
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#endif
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/* assign the global variable of SRAM model */
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assert(NULL != Arch.sram_inf.spice_sram_inf_orgz); /* Check !*/
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sram_spice_model = Arch.sram_inf.spice_sram_inf_orgz->spice_model;
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sram_spice_orgz_type = Arch.sram_inf.spice_sram_inf_orgz->type;
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/* initialize the SRAM organization information struct */
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sram_spice_orgz_info = alloc_one_sram_orgz_info();
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init_sram_orgz_info(sram_spice_orgz_info, sram_spice_orgz_type, sram_spice_model, nx + 2, ny + 2);
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/* Report error: SPICE part only support standalone SRAMs */
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if (SPICE_SRAM_STANDALONE != sram_spice_orgz_info->type) {
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vpr_printf(TIO_MESSAGE_ERROR, "Currently FPGA SPICE netlist only support standalone SRAM organization!\n");
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exit(1);
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}
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/* Check all the SRAM port is using the correct SRAM SPICE MODEL */
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config_spice_models_sram_port_spice_model(Arch.spice->num_spice_model,
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Arch.spice->spice_models,
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Arch.sram_inf.spice_sram_inf_orgz->spice_model);
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/* Assign global variables of input and output pads */
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iopad_spice_model = find_iopad_spice_model(Arch.spice->num_spice_model, Arch.spice->spice_models);
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assert(NULL != iopad_spice_model);
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/* Initial Arch SPICE MODELS*/
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/* zero the counter of each spice_model */
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zero_spice_models_cnt(Arch.spice->num_spice_model, Arch.spice->spice_models);
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/* Move to the top-level function: vpr_fpga_spice_tool_suits */
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/* init_check_arch_spice_models(&Arch, &vpr_setup.RoutingArch); */
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init_list_include_netlists(Arch.spice);
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/* Initialize the number of configuration bits of all the grids */
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init_grids_num_conf_bits(sram_spice_orgz_info);
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init_grids_num_iopads();
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/* Add keyword checking */
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/* Move to the top-level function: vpr_fpga_spice_tool_suits */
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/* check_keywords_conflict(Arch); */
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/*Process the circuit name*/
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split_path_prog_name(circuit_name,'/',&chomped_spice_dir ,&chomped_circuit_name);
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/* Update the global variable :
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* the number of mutli-thread used in SPICE simulator */
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spice_sim_multi_thread_num = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_sim_multi_thread_num;
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/* FPGA-SPICE formally starts*/
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vpr_printf(TIO_MESSAGE_INFO, "\nFPGA-SPICE starts...\n");
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/* Start Clocking*/
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t_start = clock();
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/* Format the directory path */
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if (NULL != vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_dir) {
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spice_dir_formatted = format_dir_path(vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_dir);
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} else {
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spice_dir_formatted = format_dir_path(my_strcat(format_dir_path(chomped_spice_dir),
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default_spice_dir_path));
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}
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/*Initial directory organization*/
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/* Process include directory */
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(include_dir_path) = my_strcat(spice_dir_formatted,include_dir_name);
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/* Process subckt directory */
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(subckt_dir_path) = my_strcat(spice_dir_formatted,subckt_dir_name);
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/* Check the spice folders exists if not we create it.*/
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create_dir_path(spice_dir_formatted);
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create_dir_path(include_dir_path);
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create_dir_path(subckt_dir_path);
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/* Generate Header files */
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spice_print_headers(include_dir_path, vpr_crit_path_delay, num_clocks, *(Arch.spice));
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/* Generate sub circuits: Inverter, Buffer, Transmission Gate, LUT, DFF, SRAM, MUX*/
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generate_spice_subckts(subckt_dir_path, &Arch ,&vpr_setup.RoutingArch);
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/* Print MUX testbench if needed */
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_pb_mux_testbench) {
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pb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_pb_mux_tb_dir_name);
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create_dir_path(pb_mux_testbench_dir_path);
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spice_print_mux_testbench(pb_mux_testbench_dir_path, chomped_circuit_name,
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include_dir_path, subckt_dir_path,
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rr_node_indices, num_clocks, Arch,
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SPICE_PB_MUX_TB,
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vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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}
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_cb_mux_testbench) {
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cb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_cb_mux_tb_dir_name);
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create_dir_path(cb_mux_testbench_dir_path);
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spice_print_mux_testbench(cb_mux_testbench_dir_path, chomped_circuit_name,
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include_dir_path, subckt_dir_path,
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rr_node_indices, num_clocks, Arch, SPICE_CB_MUX_TB,
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vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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}
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_sb_mux_testbench) {
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sb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_sb_mux_tb_dir_name);
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create_dir_path(sb_mux_testbench_dir_path);
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spice_print_mux_testbench(sb_mux_testbench_dir_path, chomped_circuit_name,
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include_dir_path, subckt_dir_path,
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rr_node_indices, num_clocks, Arch, SPICE_SB_MUX_TB,
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vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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}
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_cb_testbench) {
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cb_testbench_dir_path = my_strcat(spice_dir_formatted, spice_cb_tb_dir_name);
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create_dir_path(cb_testbench_dir_path);
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spice_print_cb_testbench(cb_testbench_dir_path, chomped_circuit_name,
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include_dir_path, subckt_dir_path,
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rr_node_indices, num_clocks, Arch,
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vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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}
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_sb_testbench) {
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sb_testbench_dir_path = my_strcat(spice_dir_formatted, spice_sb_tb_dir_name);
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create_dir_path(sb_testbench_dir_path);
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spice_print_sb_testbench(sb_testbench_dir_path, chomped_circuit_name,
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include_dir_path, subckt_dir_path,
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rr_node_indices, num_clocks, Arch,
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vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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}
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_lut_testbench) {
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lut_testbench_dir_path = my_strcat(spice_dir_formatted, spice_lut_tb_dir_name);
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create_dir_path(lut_testbench_dir_path);
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spice_print_lut_testbench(lut_testbench_dir_path, chomped_circuit_name, include_dir_path, subckt_dir_path,
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rr_node_indices, num_clocks, Arch, vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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}
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/* Print hardlogic testbench file if needed */
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_hardlogic_testbench) {
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hardlogic_testbench_dir_path = my_strcat(spice_dir_formatted, spice_hardlogic_tb_dir_name);
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create_dir_path(hardlogic_testbench_dir_path);
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spice_print_hardlogic_testbench(hardlogic_testbench_dir_path, chomped_circuit_name, include_dir_path, subckt_dir_path,
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rr_node_indices, num_clocks, Arch, vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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}
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/* Print Grid testbench if needed */
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_grid_testbench) {
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grid_testbench_dir_path = my_strcat(spice_dir_formatted, spice_grid_tb_dir_name);
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create_dir_path(grid_testbench_dir_path);
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spice_print_grid_testbench(grid_testbench_dir_path, chomped_circuit_name,
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include_dir_path, subckt_dir_path,
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rr_node_indices, num_clocks, Arch,
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vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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}
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/* Print Netlists of the given FPGA*/
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if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_top_testbench) {
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top_testbench_file = my_strcat(chomped_circuit_name, spice_top_testbench_postfix);
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bitstream_file_name = my_strcat(chomped_circuit_name, bitstream_spice_file_postfix);
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bitstream_file_path = my_strcat(spice_dir_formatted, bitstream_file_name);
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/* Process top_netlist_path */
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top_testbench_dir_path = my_strcat(spice_dir_formatted, spice_top_tb_dir_name);
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create_dir_path(top_testbench_dir_path);
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top_netlist_path = my_strcat(top_testbench_dir_path, top_testbench_file);
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spice_print_top_netlist(chomped_circuit_name, top_netlist_path,
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include_dir_path, subckt_dir_path,
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num_rr_nodes, rr_node, rr_node_indices, num_clocks, *(Arch.spice),
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vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only);
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/* Dump bitstream file */
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dump_fpga_spice_bitstream(bitstream_file_path, chomped_circuit_name, sram_spice_orgz_info);
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}
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/* Generate a shell script for running HSPICE simulations */
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fprint_run_hspice_shell_script(*(Arch.spice), spice_dir_formatted, subckt_dir_path);
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/* END Clocking*/
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t_end = clock();
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run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
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vpr_printf(TIO_MESSAGE_INFO, "SPICE netlists dumping took %g seconds\n", run_time_sec);
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/* Free sram_orgz_info */
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free_sram_orgz_info(sram_spice_orgz_info,
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sram_spice_orgz_info->type,
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nx + 2, ny + 2);
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/* Free tb_llist */
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free_spice_tb_llist();
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/* Free */
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my_free(spice_dir_formatted);
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my_free(include_dir_path);
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my_free(subckt_dir_path);
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return;
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}
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