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Buffer.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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FF.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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Inverter_1.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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Tapered_inverter.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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ccff_fpga.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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config_chain.svg
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[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
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2021-01-04 18:30:04 -07:00 |
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config_chain_config_enable.svg
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[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
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2021-01-04 18:30:04 -07:00 |
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config_chain_scan_capable.svg
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[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
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2021-01-04 18:30:04 -07:00 |
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config_latch.png
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update documentation about the frame-based configuration protocol
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2020-06-11 19:31:11 -06:00 |
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fabric_key_motivation.png
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[Documentation] Update documentation about the multi-region configuration
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2020-09-29 15:55:42 -06:00 |
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frac_lut3_example.svg
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[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
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2021-03-15 11:40:09 -06:00 |
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frame_config_protocol.png
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update documentation about the frame-based configuration protocol
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2020-06-11 19:31:11 -06:00 |
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frame_config_protocol_example.png
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update documentation for standalone configuration protocol
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2020-06-11 19:31:13 -06:00 |
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full_adder_1bit_circuit_model.svg
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[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
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2021-05-24 15:24:50 -06:00 |
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global_inout_ports.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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global_input_ports.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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global_tile_ports.png
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[Doc] Add illustrative example to diff between global ports definitions
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2020-11-12 09:24:39 -07:00 |
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gpin_ports.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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gpio_ports.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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gpout_ports.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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iopad.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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lut_arith_example.svg
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[Doc] Update documentation about the super LUT feature
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2021-02-10 11:49:59 -07:00 |
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lut_intermediate_buffer_example.svg
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[Doc] Add svg figures for LUT examples
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2020-11-26 12:35:39 -07:00 |
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meas_edge.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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memory_bank.png
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[Doc] update documentation about memory bank definition
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2020-10-29 17:04:25 -06:00 |
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memory_bank_decoder.svg
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[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
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2021-10-04 12:09:42 -07:00 |
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memory_bank_flatten.svg
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[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
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2021-10-04 12:09:42 -07:00 |
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memory_bank_shift_register.svg
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[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
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2021-10-04 12:09:42 -07:00 |
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multi_mode_dpram128x8_memory_circuit_model.svg
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[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
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2021-05-24 14:50:55 -06:00 |
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multi_mode_ff_circuit_model.svg
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[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
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2021-05-24 13:03:40 -06:00 |
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multi_mode_mult8x8_circuit_model.svg
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[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
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2021-05-24 15:24:50 -06:00 |
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multi_region_config_chains.png
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[Documentation] Update documentation about the multi-region configuration
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2020-09-29 15:55:42 -06:00 |
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mux.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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mux1lvl.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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native_frac_lut.svg
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[Doc] Bug fix in LUT circuit model documentation
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2020-12-04 14:44:27 -07:00 |
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pass-gate.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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pass_transistor.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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point2point_example.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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point2point_truthtable.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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single_lut3_example.svg
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[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
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2021-03-15 11:40:09 -06:00 |
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single_mode_dpram128x8_memory_circuit_model.svg
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[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
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2021-05-24 14:50:55 -06:00 |
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single_mode_mult8x8_circuit_model.svg
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[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
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2021-05-24 15:24:50 -06:00 |
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sram_blwl.png
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update documentation about the frame-based configuration protocol
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2020-06-11 19:31:11 -06:00 |
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sram_blwlr.svg
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[Doc] Add missing figures
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2021-09-20 20:31:53 -07:00 |
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std_frac_lut.svg
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[Doc] Bug fix in LUT circuit model documentation
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2020-12-04 14:44:27 -07:00 |
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thru_channel.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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vanilla_config_protocol.png
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update documentation for standalone configuration protocol
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2020-06-11 19:31:13 -06:00 |
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wire.png
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
a01fa7c282
