riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow
History
AurelienUoU 32176eb352 Adding EPFL benchmark task for openfpga_flow 2019-12-03 14:31:53 -07:00
..
SpiceNetlists Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
VerilogNetlists Adding DPRAM behavioural Verilog netlist and its TB 2019-12-03 13:58:20 -07:00
arch passing regression test on dpram benchmarks 2019-11-07 14:57:46 -07:00
benchmarks passing regression test on dpram benchmarks 2019-11-07 14:57:46 -07:00
docs Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00
misc Added task support for modelsim script 2019-11-15 23:23:15 -07:00
scripts Updated modelsim and collected result 2019-11-16 19:10:04 -07:00
tasks Adding EPFL benchmark task for openfpga_flow 2019-12-03 14:31:53 -07:00
tech Added Power Model Files 2019-08-19 18:55:23 -06:00
.gitignore Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00