tangxifan 8b17bf1b1c [test] add a new test case to validate that .act file is not required when power analysis flow is off		2022-08-01 18:44:47 -07:00
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fixed_operating_clock_freq/config	[Test] Added the dedicated test case for fixed shift register clock frequency	2021-10-06 12:09:26 -07:00
fixed_operating_clock_freq_no_ace/config	[test] add a new test case to validate that .act file is not required when power analysis flow is off	2022-08-01 18:44:47 -07:00
fixed_shift_register_clock_freq/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00