Yunus Emre ERYILMAZ f62d435b1e Update frac_mem_32k.v		2022-10-12 09:35:35 +03:00
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spice	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
spice_testbench	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
verilog	Update frac_mem_32k.v	2022-10-12 09:35:35 +03:00
verilog_testbench	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
Makefile	[test] add regression test to validate compilation of openfpga cell library files	2022-05-09 16:00:51 +08:00
verilog_sources.f	[test] add regression test to validate compilation of openfpga cell library files	2022-05-09 16:00:51 +08:00