riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow/tasks
History
tangxifan 655b195d8b [Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level 2021-09-22 15:56:44 -07:00
..
basic_tests [Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level 2021-09-22 15:56:44 -07:00
benchmark_sweep [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
ci_tests added design_variables.yml 2021-07-01 16:31:42 +05:00
compilation_verification/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_bitstream [Test] Add test cases for 'report_bitstream_distribution' command 2021-05-07 12:06:24 -06:00
fpga_sdc/sdc_time_unit [Test] Expand sdc time unit test to sweep all the available units 2021-04-11 20:14:09 -06:00
fpga_spice/generate_spice/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_verilog [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
quicklogic_tests [Test] Deploy the newly added adder benchmarks to tests 2021-06-30 15:14:24 -06:00
.gitignore Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
README.md [Doc] Update README for the regression test tasks 2021-02-22 10:17:02 -07:00

README.md

Regression tests for OpenFPGA

The regression tests are grouped in category of OpenFPGA tools as well as integrated flows. The principle is that each OpenFPGA tool should have a set of regression tests.

  • compilation_verfication: a quicktest after compilation

  • Basic regression tests should focus on fundamental flow integration, such as

    • Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run

  • FPGA-Verilog regression tests should focus on testing fabric correctness, such as

    • VPR + OpenFPGA integration for a BLIF-to-Verification flow-run

  • FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites

  • FPGA-SDC regression test should focus on SDC file generation and necessary syntax check

  • FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.

  • Quicklogic regression test is to ensure working flows for QuickLogic's devices and variants

  • Benchmark sweep regression test should focus on testing mainly the bitstream generation for a wide range of benchmark suites

Please keep this README up-to-date on the OpenFPGA tools