64 lines
1.4 KiB
ReStructuredText
64 lines
1.4 KiB
ReStructuredText
.. OpenFPGA documentation master file, created by
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sphinx-quickstart on Thu Sep 13 12:15:14 2018.
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You can adapt this file completely to your liking, but it should at least
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contain the root `toctree` directive.
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Welcome to OpenFPGA's documentation!
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====================================
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.. toctree::
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:caption: Motivation
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motivation
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.. toctree::
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:caption: Getting Started
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eda_flow
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.. toctree::
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:maxdepth: 2
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:caption: Tools Guide
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arch_lang/index
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fpga_spice/index
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fpga_verilog/index
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fpga_bitstream/index
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.. toctree::
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:maxdepth: 2
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:caption: User Guide
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tutorials/index
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.. toctree::
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:maxdepth: 2
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:caption: Appendix
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contact
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reference
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For more information on the VTR see [vtr_doc](https://docs.verilogtorouting.org/en/latest/) // [vtr_github](https://github.com/verilog-to-routing/vtr-verilog-to-routing)
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For more information on the Yosys see yosys_doc_ // yosys_github_
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For more information on the original FPGA architecture description language see xml_vtr_
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Indices and tables
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==================
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* :ref:`genindex`
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* :ref:`modindex`
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* :ref:`search`
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.. _vpr_doc: https://docs.verilogtorouting.org/en/latest/
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.. _vpr_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing
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.. _yosys_doc: http://www.clifford.at/yosys/
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.. _yosys_github: https://github.com/YosysHQ/yosys
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.. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/
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