.. OpenFPGA documentation master file, created by
   sphinx-quickstart on Thu Sep 13 12:15:14 2018.
   You can adapt this file completely to your liking, but it should at least
   contain the root `toctree` directive.

Welcome to OpenFPGA's documentation!
====================================

.. toctree::
   :caption: Motivation

   motivation

.. toctree::
   :caption: Getting Started 

   eda_flow

.. toctree::
   :maxdepth: 2
   :caption: Tools Guide

   arch_lang/index

   fpga_spice/index

   fpga_verilog/index

   fpga_bitstream/index

.. toctree::
   :maxdepth: 2
   :caption: User Guide

   tutorials/index

.. toctree::
   :maxdepth: 2
   :caption: Appendix
  
   contact
   reference
   
For more information on the VTR see [vtr_doc](https://docs.verilogtorouting.org/en/latest/) // [vtr_github](https://github.com/verilog-to-routing/vtr-verilog-to-routing) 

For more information on the Yosys see yosys_doc_ // yosys_github_

For more information on the original FPGA architecture description language see xml_vtr_



Indices and tables
==================

* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`

.. _vpr_doc: https://docs.verilogtorouting.org/en/latest/
.. _vpr_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing
.. _yosys_doc: http://www.clifford.at/yosys/
.. _yosys_github: https://github.com/YosysHQ/yosys
.. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/