History

tangxifan 33a253da3d [core] fixed the bug		2024-09-20 22:20:41 -07:00
..
basic_tests	[core] fixed the bug	2024-09-20 22:20:41 -07:00
benchmark_sweep	[test] relax minW for counter128, as VPR's router degrades in routability	2022-11-03 19:48:13 -07:00
compilation_verification/config	…
fpga_bitstream	Pass in the OpenFPGA root dir	2024-07-29 11:04:03 -07:00
fpga_sdc/sdc_time_unit	[Test] Expand sdc time unit test to sweep all the available units	2021-04-11 20:14:09 -06:00
fpga_spice/generate_spice/config	…
fpga_verilog	[test] validate mux2 at last stage	2024-09-18 17:40:13 -07:00
quicklogic_tests	[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases	2022-09-29 10:45:27 -07:00
template_tasks	renamed yosys_vpr_template fabric_netlist_gen_template	2023-02-11 18:33:06 -07:00
.gitignore	…
README.md	…

README.md

Regression tests for OpenFPGA

The regression tests are grouped in category of OpenFPGA tools as well as integrated flows. The principle is that each OpenFPGA tool should have a set of regression tests.

compilation_verfication: a quicktest after compilation
Basic regression tests should focus on fundamental flow integration, such as
- Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run
FPGA-Verilog regression tests should focus on testing fabric correctness, such as
- VPR + OpenFPGA integration for a BLIF-to-Verification flow-run
FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites
FPGA-SDC regression test should focus on SDC file generation and necessary syntax check
FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.
Quicklogic regression test is to ensure working flows for QuickLogic's devices and variants
Benchmark sweep regression test should focus on testing mainly the bitstream generation for a wide range of benchmark suites

Please keep this README up-to-date on the OpenFPGA tools