83 lines
2.6 KiB
C++
83 lines
2.6 KiB
C++
/********************************************************************
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* This file includes functions to generate SPICE subcircuits for LUTs
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********************************************************************/
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#include <string>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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#include "mux_graph.h"
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#include "module_manager.h"
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#include "mux_utils.h"
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#include "openfpga_naming.h"
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#include "spice_constants.h"
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#include "spice_writer_utils.h"
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#include "spice_subckt_writer.h"
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#include "spice_lut.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print SPICE modules for the Look-Up Tables (LUTs)
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* in the circuit library
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********************************************************************/
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int print_spice_submodule_luts(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::string& submodule_dir) {
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int status = CMD_EXEC_SUCCESS;
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std::string spice_fname = submodule_dir + std::string(LUTS_SPICE_FILE_NAME);
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std::fstream fp;
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/* Create the file stream */
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fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
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/* Check if the file stream if valid or not */
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check_file_stream(spice_fname.c_str(), fp);
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/* Create file */
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VTR_LOG("Writing SPICE netlist for LUTs '%s'...",
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spice_fname.c_str());
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print_spice_file_header(fp, "Look-Up Tables");
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/* Search for each LUT circuit model */
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for (const auto& lut_model : circuit_lib.models()) {
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/* Bypass user-defined and non-LUT modules */
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if ( (!circuit_lib.model_spice_netlist(lut_model).empty())
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|| (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) ) {
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continue;
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}
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/* Find the module id */
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ModuleId lut_module = module_manager.find_module(circuit_lib.model_name(lut_model));
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VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
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write_spice_subckt_to_file(fp, module_manager, lut_module);
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}
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/* Close the file handler */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
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VTR_ASSERT(NetlistId::INVALID() != nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
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VTR_LOG("Done\n");
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return status;
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}
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} /* end namespace openfpga */
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