125 lines
4.2 KiB
Verilog
125 lines
4.2 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Mixcolumns for a 16 bit word module implementation ////
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//// ////
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//// This file is part of the SystemC AES ////
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//// ////
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//// Description: ////
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//// Mixcolum for a 16 bit word ////
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//// ////
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//// Generated automatically using SystemC to Verilog translator ////
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//// ////
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//// To Do: ////
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//// - done ////
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//// ////
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//// Author(s): ////
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//// - Javier Castillo, jcastilo@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: word_mixcolum.v,v $
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// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo
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// First import
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//
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module word_mixcolum(in,outx,outy);
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input [31:0] in;
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output [31:0] outx;
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output [31:0] outy;
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reg [31:0] outx;
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reg [31:0] outy;
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reg [7:0] a;
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reg [7:0] b;
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reg [7:0] c;
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reg [7:0] d;
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wire [7:0] x1;
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wire [7:0] x2;
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wire [7:0] x3;
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wire [7:0] x4;
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wire [7:0] y1;
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wire [7:0] y2;
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wire [7:0] y3;
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wire [7:0] y4;
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byte_mixcolum bm1 (.a(a), .b(b), .c(c), .d(d), .outx(x1), .outy(y1));
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byte_mixcolum bm2 (.a(b), .b(c), .c(d), .d(a), .outx(x2), .outy(y2));
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byte_mixcolum bm3 (.a(c), .b(d), .c(a), .d(b), .outx(x3), .outy(y3));
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byte_mixcolum bm4 (.a(d), .b(a), .c(b), .d(c), .outx(x4), .outy(y4));
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reg[31:0] in_var;
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reg[31:0] outx_var,outy_var;
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//split:
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always @( in)
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begin
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in_var=in;
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a = (in_var[31:24]);
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b = (in_var[23:16]);
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c = (in_var[15:8]);
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d = (in_var[7:0]);
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end
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//mix:
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always @( x1 or x2 or x3 or x4 or y1 or y2 or y3 or y4)
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begin
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outx_var[31:24]=x1;
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outx_var[23:16]=x2;
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outx_var[15:8]=x3;
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outx_var[7:0]=x4;
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outy_var[31:24]=y1;
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outy_var[23:16]=y2;
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outy_var[15:8]=y3;
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outy_var[7:0]=y4;
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outx = (outx_var);
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outy = (outy_var);
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end
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endmodule
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