OpenFPGA/libopenfpga/libpinconstrain/data/pinmap_k4_N4_tileable_40nm.csv

1	orientation	row	col	pin_num_in_cell	port_name	mapped_pin	GPIO_type	Associated Clock	Clock Edge
2	TOP				gfpga_pad_IO_A2F[0]	pad_fpga_io[0]
3	TOP				gfpga_pad_IO_F2A[0]	pad_fpga_io[0]
4	TOP				gfpga_pad_IO_A2F[4]	pad_fpga_io[1]
5	TOP				gfpga_pad_IO_F2A[4]	pad_fpga_io[1]
6	TOP				gfpga_pad_IO_A2F[8]	pad_fpga_io[2]
7	TOP				gfpga_pad_IO_F2A[8]	pad_fpga_io[2]
8	TOP				gfpga_pad_IO_A2F[31]	pad_fpga_io[3]
9	TOP				gfpga_pad_IO_F2A[31]	pad_fpga_io[3]
10	RIGHT				gfpga_pad_IO_A2F[32]	pad_fpga_io[4]
11	RIGHT				gfpga_pad_IO_F2A[32]	pad_fpga_io[4]
12	RIGHT				gfpga_pad_IO_A2F[40]	pad_fpga_io[5]
13	RIGHT				gfpga_pad_IO_F2A[40]	pad_fpga_io[5]
14	BOTTOM				gfpga_pad_IO_A2F[64]	pad_fpga_io[6]
15	BOTTOM				gfpga_pad_IO_F2A[64]	pad_fpga_io[6]
16	LEFT				gfpga_pad_IO_F2A[127]	pad_fpga_io[7]
17	LEFT				gfpga_pad_IO_A2F[127]	pad_fpga_io[7]