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adder
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[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
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2022-09-29 10:45:27 -07:00 |
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bram
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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depopulate_crossbar/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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dsp
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[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
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2022-09-29 10:45:27 -07:00 |
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duplicated_grid_pin/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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fabric_chain
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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flatten_routing/config
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[Test] Deploy default net type option to test case
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2021-02-28 12:20:43 -07:00 |
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fully_connected_output_crossbar/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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io
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[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
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2022-09-29 10:45:27 -07:00 |
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lut_design
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[test] now use a fixed device layout for the single-mode LUT design testcase
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2022-10-04 10:05:22 -07:00 |
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mux_design
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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power_gated_design/power_gated_inverter/config
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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spypad/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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thru_channel
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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untileable/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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verilog_netlist_formats
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[Test] Fix bugs on the remaining implicit verilog test cases
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2022-02-15 16:49:15 -08:00 |
ab53f88c2b