tangxifan e34380a654 Merge branch 'master' into default_net_type		2021-03-01 08:38:58 -07:00
..
annotation	[Tool] Add bitstream annotation support	2021-02-01 20:49:36 -07:00
base	[Tool] Support default_net_type Verilog syntex in fabric generator	2021-02-28 11:57:40 -07:00
fabric	[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition	2021-02-18 21:56:30 -07:00
fpga_bitstream	[Tool] Support superLUT circuit model in core engine	2021-02-09 20:23:05 -07:00
fpga_sdc	[Tool] Support superLUT circuit model in core engine	2021-02-09 20:23:05 -07:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1	2021-02-28 17:04:27 -07:00
mux_lib	[Tool] Support superLUT circuit model in core engine	2021-02-09 20:23:05 -07:00
repack	[Tool] Patch repacker to support duplicated nets due to adder nets	2021-02-23 19:01:18 -07:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Use dedicated function to identify wire LUT created by repacker	2021-02-18 19:37:44 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00