tangxifan f8845f7d3a [Test] Add a test case to validate separated clock pins in global port		2022-03-20 11:02:07 +08:00
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global_tile_4clock/config	[Test] Adapt pin constraints due to changes in pin names	2022-02-15 16:06:46 -08:00
global_tile_4clock_pin/config	[Test] Add a test case to validate separated clock pins in global port	2022-03-20 11:02:07 +08:00
global_tile_clock/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
global_tile_reset/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00