Baudouin Chauviere 0ce9846e47 Stable, unfinished		2019-06-26 16:54:41 -06:00
..
base	fixed the bug in determine passing wires for rr_gsb	2019-06-26 10:50:23 -06:00
bitstream	fixed the bug in determine passing wires for rr_gsb	2019-06-26 10:50:23 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	bug fixing for memory leaking in allocating pb_rr_graph and power estimation	2019-06-15 12:23:36 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	fix a bug for iopad SPICE generation	2019-06-11 11:43:56 -06:00
verilog	Stable, unfinished	2019-06-26 16:54:41 -06:00