tangxifan 066962fbb9 bug fixed for clb2clb direct connection		2019-11-05 17:41:21 -07:00
..
base	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
bitstream	critical bug fixed for bitstream generation for offset truth tables	2019-10-31 20:16:08 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	bug fixed for clb2clb direct connection	2019-11-05 17:41:21 -07:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	added Verilog generation for preconfig top module	2019-10-29 13:54:35 -06:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	remove useless channel wire module generation	2019-11-05 16:10:00 -07:00