tangxifan bba476fef4 add explicit port mapping support to Verilog testbench generator		2020-06-11 19:31:07 -06:00
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configuration_chain_example_script.openfpga	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
duplicated_grid_pin_example_script.openfpga	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
example_script.openfpga	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
flatten_routing_example_script.openfpga	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
generate_fabric_example_script.openfpga	massively deploy disable_timing for configure ports in CI	2020-06-11 19:31:06 -06:00
generate_testbench_example_script.openfpga	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
implicit_verilog_example_script.openfpga	massively deploy disable_timing for configure ports in CI	2020-06-11 19:31:06 -06:00
mcnc_example_script.openfpga	massively deploy disable_timing for configure ports in CI	2020-06-11 19:31:06 -06:00
sdc_time_unit_example_script.openfpga	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00