CHARAS SAMY 0020fe42bf Reverted changes to test_mode_low.		2020-05-11 12:17:45 -06:00
..
OpenFPGAShellScripts	add testcases on generate fabric/testbench only	2020-04-28 18:22:41 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	add register chain and scan chain to Travis CI	2020-04-12 15:28:22 -06:00
arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
benchmarks	Reverted changes to test_mode_low.	2020-05-11 12:17:45 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Fixed modelsim include references	2020-04-24 21:53:57 -06:00
openfpga_arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
scripts	BugFix : Relative path for refrence benchmark fixed	2020-04-25 20:16:17 -06:00
sva	Modified testbenches according to new arch.	2020-05-11 11:46:03 -06:00
tasks	Adding decoder task	2020-05-01 15:56:05 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00