coolbreeze413 cbbb4435b0 leverage yosys-symbiflow-plugins configurable YOSYS_CONFIG param to leave OpenFPGA yosys build structure untouched		2021-10-13 21:47:03 +05:30
..
formality_template.tcl	Updated formality python script	2019-09-27 14:00:57 -06:00
fpgaflow_default_tool_path.conf	leverage yosys-symbiflow-plugins configurable YOSYS_CONFIG param to leave OpenFPGA yosys build structure untouched	2021-10-13 21:47:03 +05:30
modelsim_proc.tcl	Added task support for modelsim script	2019-11-15 23:23:15 -07:00
modelsim_runsim.tcl	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
qlf_yosys.ys	restore build.yml	2021-09-07 04:48:44 -07:00
ys_tmpl_rewrite_flow.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00
ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys	remove opt_rmdff as it has been deprecated with the new yosys versions	2021-10-13 05:08:26 +05:30
ys_tmpl_yosys_vpr_bram_dsp_flow.ys	remove opt_rmdff as it has been deprecated with the new yosys versions	2021-10-13 05:08:26 +05:30
ys_tmpl_yosys_vpr_bram_flow.ys	remove opt_rmdff as it has been deprecated with the new yosys versions	2021-10-13 05:08:26 +05:30
ys_tmpl_yosys_vpr_dff_flow.ys	[Script] Patch yosys script with dff tech map	2021-04-16 20:47:18 -06:00
ys_tmpl_yosys_vpr_dsp_flow.ys	remove opt_rmdff as it has been deprecated with the new yosys versions	2021-10-13 05:08:26 +05:30
ys_tmpl_yosys_vpr_flow.ys	Added fpga_flow script - Working Yosys	2019-08-09 16:49:05 -06:00
ys_tmpl_yosys_vpr_flow_with_rewrite.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00