victorzh001 04a60ca4b5 Merge branch 'master' into victor_OpenFPGA_dbg		2024-09-10 11:01:47 +08:00
..
arch_bitstreams	…
benchmarks	[core] typo	2024-07-10 14:12:49 -07:00
docs	…
fabric_keys	[test] deploy new tests	2023-07-08 21:52:16 -07:00
misc	[script] typo	2023-12-12 13:45:23 -08:00
openfpga_arch	[test] typo	2024-08-09 17:05:48 -07:00
openfpga_cell_library	…
openfpga_shell_scripts	Merge branch 'master' into victor_OpenFPGA_dbg	2024-09-10 11:01:47 +08:00
openfpga_simulation_settings	…
openfpga_yosys_techlib	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
regression_test_scripts	Merge branch 'master' into victor_OpenFPGA_dbg	2024-09-10 11:01:47 +08:00
scripts	[script] adapt code format for python	2024-04-10 12:58:05 -07:00
tasks	Merge branch 'master' into victor_OpenFPGA_dbg	2024-09-10 11:01:47 +08:00
tech	…
vpr_arch	[test] add a new test to validate CHANY clock spin in DEC	2024-08-15 14:24:31 -07:00
.gitignore	…