tangxifan efdb8bf441 [test] use fixed route chan width to avoid the bug on vpr which failed routing on min chan width condition		2024-10-07 17:14:11 -07:00
..
adder	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
bram	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
depopulate_crossbar/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
dsp	[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases	2022-09-29 10:45:27 -07:00
duplicated_grid_pin/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
fabric_chain	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
flatten_routing/config	[Test] Deploy default net type option to test case	2021-02-28 12:20:43 -07:00
fully_connected_output_crossbar/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
io	[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases	2022-09-29 10:45:27 -07:00
lut_design	[test] fixed the bug in single-mode lut testcase	2023-11-14 09:35:26 -08:00
mux_design	[test] use fixed route chan width to avoid the bug on vpr which failed routing on min chan width condition	2024-10-07 17:14:11 -07:00
power_gated_design/power_gated_inverter/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
rr_concat_wire/config	[test] add new testcase	2023-11-13 14:11:34 -08:00
spypad/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
thru_channel	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
untileable/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
verilog_netlist_formats	[test] add new tests to validate the options for undriven inputs in verilog netlists	2024-08-06 20:58:00 -07:00