4 Commits

Author	SHA1	Message	Date
tangxifan	b6bb433edc	bug fixing for datapath mux size in Verilog generation	2019-09-03 18:09:21 -06:00
tangxifan	bee070d7cc	start plug in MUX library	2019-08-20 15:24:53 -06:00
tangxifan	dcca9f4f0f	finish mux graph builders	2019-08-20 15:24:52 -06:00
tangxifan	638969c3c9	adding mux graph data structures	2019-08-20 15:24:52 -06:00