4 Commits

Author	SHA1	Message	Date
tangxifan	c6c3ef71f3	adapt all the Verilog submodule writers and bring it onlien	2020-02-16 13:35:18 -07:00
tangxifan	622c7826d1	start transplanting fpga_verilog	2020-02-15 15:03:00 -07:00
tangxifan	3ace7f8ef7	move generic data structures to openfpgautil library	2020-01-16 13:26:55 -07:00
tangxifan	d232391250	developed XML writer for circuit library and start porting functions to openfpgautil library	2020-01-16 12:32:29 -07:00