tangxifan
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95863e996a
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minor update on arch to use auto layout sizing
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2020-04-18 18:43:56 -06:00 |
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tangxifan
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2f3a36ee81
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update timing and rename the arch file
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2020-04-18 18:39:47 -06:00 |
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tangxifan
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7ce34be175
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update sample architecture timing
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2020-04-17 22:06:06 -06:00 |
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tangxifan
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2ea4b8a2a2
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add more flagship architectures
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2020-04-17 19:12:27 -06:00 |
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tangxifan
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2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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214d98fbcd
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add register chain and scan chain to Travis CI
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2020-04-12 15:28:22 -06:00 |
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tangxifan
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148cc74d6a
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add io test cases to Travis CI
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2020-04-12 15:01:47 -06:00 |
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tangxifan
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da5af8f0e0
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try to add aib test case. bug found
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2020-04-12 14:54:45 -06:00 |
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tangxifan
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600a48edc7
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add test case of BRAM to Travis CI
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2020-04-12 14:27:05 -06:00 |
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tangxifan
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68fd296e14
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add more test vpr architecture to regression tests
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2020-04-12 12:49:16 -06:00 |
ganeshgore
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eb3b02277a
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Added XML and benchmarks for testing
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2020-04-06 00:32:06 -06:00 |