4 Commits

Author	SHA1	Message	Date
tangxifan	15e26a5602	[Tool] Support default_net_type Verilog syntex in fabric generator	2021-02-28 11:57:40 -07:00
tangxifan	8f5a684b10	removed redundant include files in all the verilog netlists except the top one	2020-06-11 19:28:13 -06:00
tangxifan	e811f8bb21	plug in netlist manager and now the include_netlist appears in one unique file	2020-04-23 20:42:11 -06:00
tangxifan	c9d8120ae0	adapt Verilog mux writer	2020-02-16 12:35:41 -07:00