tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
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tangxifan
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15e26a5602
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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tangxifan
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6bdfcb0147
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[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
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tangxifan
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6f18688f0e
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[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
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2020-12-05 10:53:01 -07:00 |
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tangxifan
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0da92ad888
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[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
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2020-12-04 22:16:51 -07:00 |
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tangxifan
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8f5a684b10
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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c9d8120ae0
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adapt Verilog mux writer
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2020-02-16 12:35:41 -07:00 |