4 Commits

Author	SHA1	Message	Date
tangxifan	d526f08782	deploy bitstream reader in openfpga shell	2020-06-20 18:48:19 -06:00
tangxifan	068d9943e7	update all the templates and regression test cases with simulation settings	2020-06-11 19:31:16 -06:00
tangxifan	96b58dfdbb	use new simulation setting command in openfpga shell	2020-06-11 19:31:15 -06:00
tangxifan	8b3e79766c	add fast configuration option to fpga_verilog to speed up full testbench simulation	2020-06-11 19:31:12 -06:00