5 Commits

Author	SHA1	Message	Date
tangxifan	6f42aac626	add wire connection in Verilog module declaration	2019-10-08 20:14:38 -06:00
tangxifan	1e187f3d15	start adding memory circuit to Switch blocks	2019-09-27 18:08:37 -06:00
tangxifan	79fa858f36	remove unused ports for Verilog modules	2019-09-11 19:39:59 -06:00
tangxifan	2bed51bf29	minor bug fix for echo	2019-09-11 17:41:45 -06:00
tangxifan	0399319212	refactored LUT Verilog generation	2019-09-11 17:04:43 -06:00