tangxifan
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6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
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3a708cff21
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[Tool] Bug fix to enable nature fracturable LUT design
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2020-11-25 23:01:18 -07:00 |
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tangxifan
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83e26adf90
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add module usage types for future FPGA-SPICE development
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2020-07-04 22:33:54 -06:00 |
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tangxifan
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e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
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cf440f92d3
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put routing module builder util function online
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2020-02-13 16:05:23 -07:00 |
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tangxifan
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e842150cc5
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add lut module builder
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2020-02-12 19:52:41 -07:00 |