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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 8915d10d27 add verbose output option to configure port disable timing writer 2020-06-11 19:31:07 -06:00
tangxifan 13f591cacf add new command to disable timing for configure ports of programmable modules 2020-06-11 19:31:06 -06:00