Aur??Lien ALACCHI
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75d64db0f9
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Add verilog header sub_module.v file generation
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2018-12-04 18:42:47 -07:00 |
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Aur??Lien ALACCHI
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8ac566ecc0
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Add timing and initialization for simulation
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2018-12-04 17:32:09 -07:00 |
tangxifan
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70751551b5
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fix a bug in wired LUT support
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2018-11-30 21:33:31 -07:00 |
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tangxifan
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e223868df8
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fix bugs for wired LUTs
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2018-11-27 12:46:30 -07:00 |
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Aur??Lien ALACCHI
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de2bc18bbb
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bugs fixed for shift register benchmark
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2018-11-26 16:58:45 -07:00 |
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tangxifan
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861c449606
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support wired LUT in FPGA-SPICE and FPGA-Verilog
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2018-11-15 15:57:49 -07:00 |
Baudouin Chauviere
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f7d7a056da
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Modification of the fpga_spice_utils
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2018-11-15 14:11:55 -07:00 |
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Baudouin Chauviere
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c81d00bb51
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Correction of the double free bug
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2018-11-15 13:55:16 -07:00 |
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tangxifan
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c67ba5f58a
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clean up codes
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2018-09-27 14:26:08 -06:00 |
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tangxifan
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681cca99a4
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fix a bug in tapbuf
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2018-09-21 19:00:22 -06:00 |
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tangxifan
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d683134b12
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |