Baudouin Chauviere
|
a5a1a376ab
|
Modified code for cleaner delay naming convention
|
2019-05-06 12:52:49 -06:00 |
|
Baudouin Chauviere
|
e7b1d89985
|
Change syntax name for loop_breaker_delay_before/after which is more explicit
|
2019-05-06 12:25:26 -06:00 |
|
Baudouin Chauviere
|
7c257ebda7
|
Fix on the makefile which was not targetting the right folder
|
2019-05-06 12:21:53 -06:00 |
tangxifan
|
6e6ae1cc3d
|
fixed bugs in CMakeLists.txt and Makefile
|
2019-05-03 23:03:04 -06:00 |
|
tangxifan
|
4e3487b691
|
Add latest abc and update ace dependence
|
2019-05-03 18:56:03 -06:00 |
|
tangxifan
|
70b66e0799
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-03 14:22:20 -06:00 |
|
Baudouin Chauviere
|
7860042276
|
added before after loop breaker constraining
|
2019-05-03 14:00:06 -06:00 |
|
tangxifan
|
11cf30b239
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-03 11:54:35 -06:00 |
|
tangxifan
|
5a97e3e602
|
update Makefile t
|
2019-05-03 11:48:41 -06:00 |
|
Baudouin Chauviere
|
921b694400
|
Bug fix sdc breaking loop of edges outside current interconnect
|
2019-05-03 10:42:35 -06:00 |
|
tangxifan
|
c46c0fc97d
|
bug fixing for SDC generator
|
2019-04-26 14:07:44 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
Aur??Lien ALACCHI
|
8ac566ecc0
|
Add timing and initialization for simulation
|
2018-12-04 17:32:09 -07:00 |
Aurelien Alacchi
|
e0c2fc2c8a
|
Documentation_code&example_update
|
2018-10-12 15:50:09 -06:00 |
|
tangxifan
|
d683134b12
|
rename customized vpr7 to vpr7 XML to Production
|
2018-09-17 23:10:45 -06:00 |