4 Commits

Author	SHA1	Message	Date
tangxifan	5368485bd6	keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level	2020-06-11 19:31:14 -06:00
tangxifan	fa8dfc1fbd	add configuration protocol ports to top module for memory bank organization	2020-06-11 19:31:13 -06:00
tangxifan	ed2325ec9e	add frame decoder build-up to top-level module	2020-06-11 19:31:09 -06:00
tangxifan	c855ab24f5	put build top module memory connections online	2020-02-14 11:07:04 -07:00