tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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af4cc117fb
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[Tool] bug fix in spypad lut
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2021-02-09 22:53:18 -07:00 |
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tangxifan
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6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
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6bdfcb0147
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[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
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tangxifan
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6f18688f0e
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[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
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2020-12-05 10:53:01 -07:00 |
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tangxifan
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83e26adf90
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add module usage types for future FPGA-SPICE development
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2020-07-04 22:33:54 -06:00 |
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tangxifan
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e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
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cf440f92d3
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put routing module builder util function online
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2020-02-13 16:05:23 -07:00 |
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tangxifan
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fddd3c9463
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add mux module builder
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2020-02-12 19:45:14 -07:00 |