This website requires JavaScript.
Explore
Help
Sign In
riscv
/
OpenFPGA
mirror of
https://github.com/lnis-uofu/OpenFPGA.git
Watch
1
Star
0
Fork
You've already forked OpenFPGA
0
Code
Issues
Projects
Releases
Wiki
Activity
543
Commits
70
Branches
8
Tags
105
MiB
c8ceb8f7d5
Commit Graph
3 Commits
Author
SHA1
Message
Date
tangxifan
95674c4687
added Switch Block SubType and SubFs for tileable rr_graph generation
2019-07-02 10:00:02 -06:00
tangxifan
548242b368
plug-in tileable rr generator which can be enable by a XML property
2019-06-20 21:06:26 -06:00
tangxifan
d683134b12
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00