tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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b9aac3cbdf
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updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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c696e3d20f
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refine frame-based memory addition to compact the area
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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ed2325ec9e
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add frame decoder build-up to top-level module
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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290dd1a8a6
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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63306ce3a0
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add comments to explain the memory organization in the top-level module
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2020-04-01 11:05:30 -06:00 |
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tangxifan
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c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |